Physical Design Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Qualcomm is looking for Physical Design Engineers to join their SoC and ASIC Design team. Responsibilities include executing all stages of the physical design flow, developing solutions for complex ASICs and SoCs, and collaborating with cross-functional teams. This role requires a Bachelor's or Master's degree and 2-10+ years of experience in Physical Design.

Responsibilities

Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs.
Perform floorplanning, partitioning, power planning, and IR-drop analysis.
Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios.
Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
Perform RC extraction, physical verification, and formal verification activities.
Implement engineering change orders (ECOs) and support design convergence through sign-off.
Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful project execution.
Contribute to the development of innovative low-power implementation methodologies and customized place-and-route solutions.
Develop automation and productivity tools using scripting languages and software development techniques.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
2-10+ years of industry experience or relevant academic/project experience in Physical Design.
Experience in ASIC/SoC Physical Design implementation.
Experience with Place and Route using Cadence Innovus and/or Synopsys Fusion Compiler.
Experience with Static Timing Analysis and timing closure using Synopsys PrimeTime SI.
Experience with Physical verification and design sign-off methodologies.
Experience with Formal verification techniques and tools.
Experience with Power domain implementation and low-power design methodologies.
Experience with Clock Tree Synthesis (CTS), routing, and timing optimization.
Low power implementation techniques experience
Experience with Signal integrity, noise analysis, and MMMC sign-off flows.
DFT-aware physical implementation and constraint management.
Programming and automation using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments.
Perl/Tcl, Python skills are needed.
Strong problem solving and ASIC development/debugging skills.

Desired Qualifications

Experience in one or more of the following areas: ASIC/SoC Physical Design implementation.
Place and Route using Cadence Innovus and/or Synopsys Fusion Compiler.
Static Timing Analysis and timing closure using Synopsys PrimeTime SI.
Physical verification and design sign-off methodologies.
Formal verification techniques and tools.
Power domain implementation and low-power design methodologies.
Clock Tree Synthesis (CTS), routing, and timing optimization.
Low power implementation techniques experience
Signal integrity, noise analysis, and MMMC sign-off flows.
DFT-aware physical implementation and constraint management.
Programming and automation using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments.
Perl/Tcl, Python skills are needed.
Strong problem solving and ASIC development/debugging skills.

Benefits

Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package designed to support your success at work, at home, and at play.