NOC DV Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Qualcomm is seeking a skilled Design Verification Engineer for NOC IPs/Sub-systems in Bangalore, India. The role involves leading verification efforts for complex AI, Networking, Datacenter, and HPC components, requiring expertise in SystemVerilog, UVM, and various high-speed protocols. A strong background in hardware engineering and protocol verification is essential.

Responsibilities

Lead verification of complex AI, Networking, Datacenter, HPC, and Interconnect IPs/Sub-systems.
Build reusable verification environments, UVCs/agents, sequences, scoreboards, checkers, assertions, and coverage infrastructure using SystemVerilog and UVM.
Develop verification plans, utilize constrained-random verification, SVA, and manage functional coverage closure and regressions.
Independently own and execute IP/Sub-System DV from specification review to verification closure.
Debug RTL, protocol, architecture, performance, and testbench issues with root-cause analysis.
Verify NoC, coherent/non-coherent interconnects, memory/cache subsystems, AI accelerators, or complex data movement fabrics.
Perform deep protocol verification in PCIe (Gen4/5/6), USB (USB3.x/USB4), Ethernet (10G/25G/100G/400G+), CXL, or other high-speed serial/networking protocols.
Verify AI Scale-Up / Scale-Out Interconnects such as UAL, UMAC, eSUN, or equivalent accelerator cluster fabrics.
Validate AMBA protocols (AXI, AHB, ACE, CHI) and coherency architectures.
Conduct performance verification, QoS validation, congestion analysis, scalability testing, and system-level qualification.
Use Python, Shell, Perl, or Tcl for regression automation, infrastructure development, and productivity enhancement.
Work with industry-standard simulators, debug tools, coverage tools, CI/CD workflows, emulation, and verification automation frameworks.

Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience; OR Master's degree and 2+ years of experience; OR PhD and 1+ year of experience.
Expert in SystemVerilog (SV) and UVM.
Hands-on experience in building reusable verification environments, UVCs/agents, sequences, scoreboards, checkers, assertions, and coverage infrastructure.
Strong expertise in verification planning, constrained-random verification, SVA, functional coverage closure, regression management, and signoff methodologies.
Proven ability to independently own and execute IP/Sub-System DV from specification review to verification closure.
Strong debugging skills across RTL, protocol, architecture, performance, and testbench issues, with demonstrated root-cause analysis capability.
Experience in verifying NoC, coherent/non-coherent interconnects, memory/cache subsystems, AI accelerators, or complex data movement fabrics.
Deep protocol verification expertise in one or more of: PCIe (Gen4/5/6), USB (USB3.x/USB4), Ethernet (10G/25G/100G/400G+), CXL, or other high-speed serial/networking protocols.
Experience with AI Scale-Up / Scale-Out Interconnects such as UAL, UMAC, eSUN, or equivalent accelerator cluster fabrics.
Strong understanding of AMBA protocols (AXI, AHB, ACE, CHI) and coherency architectures.
Knowledge of performance verification, QoS validation, congestion analysis, scalability testing, and system-level qualification.
Proficiency in Python, Shell, Perl, or Tcl for regression automation, infrastructure development, and productivity enhancement.
Familiarity with industry-standard simulators, debug tools, coverage tools, CI/CD workflows, emulation, and verification automation frameworks.
Strong collaboration, communication, technical leadership, and execution skills.

Desired Qualifications

Verification experience in SoC, AI/ML Accelerators, Networking, Datacenter, Multi-Die, or HPC platforms.
Exposure to SystemC/TLM modeling, performance modeling, emulation/prototyping, and post-silicon correlation.
Track record of delivering first-pass verification closure for complex IPs and subsystems.
B.Tech/M.Tech in Electronics, Electrical Engineering, Computer Science, VLSI, or related disciplines from reputed Tier-1 institutions (IITs, NITs, IIITs, BITS, or equivalent).
Relevant industry experience aligned with the position level, demonstrating strong expertise in Design Verification, SV/UVM methodologies, protocol verification, and architecture-driven validation.
Proven history of technical ownership and successful delivery of complex IP, Sub-System, or SoC verification programs.