NOC Design Verification Sr Lead Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing

In short

Qualcomm is looking for an experienced NOC Design Verification Sr Lead Engineer in Bangalore to be responsible for verification of next-generation Infrastructure IPs. This role involves planning and implementing verification flows, coordinating with design teams, and ensuring quality sign-off.

Responsibilities

Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage)
Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench
Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure
Debug of regression signatures and identifying bug fixes
Responsible for Quality sign off and required documentation
Developing/Deploying scripts/tools for validation (Certitude, VC Formal, VPlan)
Debug and root cause post silicon issues in collaboration with Design, SW and test teams
Work with SoC level performance modeling team on latency, bandwidth analysis

Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
Strong debugging, Analytical and problem-solving skills
Expertise on UVM based verification
Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture
Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved
Communication and collaboration skills to work with a large world-wide design organization
3+ Years of Experience in IP verification or related
Experience with UVM and ARM Bus protocols.

Desired Qualifications

Experience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse
Experience in verifying designs meeting Automotive Safety Integrity Levels (ASIL)
Proficiency in Scripting languages (Python or Perl) for Automation initiatives, C/C++/SystemC for performance models
Post-si bring-up and HW-SW debug experience would be a plus.
Knowledge & exposure to silicon debug tool chains would be an added advantage