Master Thesis: IP-Level Shift-Left RTL Power Analysis Flow for Early Power Insight and Optimization

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

This Master Thesis project focuses on evaluating a "shift-left" RTL power analysis methodology using Synopsys RTLA and PrimePower RTL to gain early power insights and optimize ASIC IPs. The goal is to assess relative accuracy, runtime reduction, and the fidelity of power metrics compared to traditional flows.

Responsibilities

  • Evaluate RTLA/PPRTL2.0 hybrid and logical flows for shift-left RTL power analysis.
  • Assess relative accuracy and trend fidelity versus full netlist-based flows.
  • Analyze runtime reduction by avoiding full implementation and GLS.
  • Evaluate fidelity for glitch power and ability to track power impact of RTL/datapath changes.
  • Assess quality of metrics extraction and RTL cross-probing for power-bug hunting.
  • Characterize vector-based and vectorless analysis, including metrics extraction and vectorless flow.
  • Analyze RTLA pseudo-netlist to real (Fusion Compiler) netlist alignment.
  • Deliver a documented, reproducible methodology and flow setup for RTLA/PPRTL 2.0.

Requirements

  • Master's student in Electrical/Computer Engineering, Computer Science or similar.
  • Background in ASIC design.
  • RTL HDL coding.
  • Testbench design using SystemVerilog.
  • Working knowledge of UVM.
  • Scripting (Tcl/Python) for EDA tools is preferred.

Benefits

  • Outstanding opportunity to use skills and imagination to push the boundaries of what's possible.
  • Build solutions never seen before to some of the world's toughest problems.
  • Challenged but not alone; joining a team of diverse innovators.
  • Opportunity to craft what comes next.
  • Encouraging a diverse and inclusive organization.
  • Championing diversity and inclusion in everything we do.
  • Belief that collaborating with people with different experiences drives innovation.
  • Encouragement for people from all backgrounds to apply and realize their full potential.
  • Ericsson is proud to be an Equal Opportunity Employer.
#Master Thesis#Power Analysis#RTL#ASIC Design#Stockholm#Sweden
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Company

Ericsson

Job Posted

1 day ago

Employment Type

Internship

WorkMode

On Site

Experience Level

Student

Locations

Stockholm, Sweden

Qualification

Master

Applicants

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