Lead Engineer/ Staff – RISCV Subsystem RTL Design
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Qualcomm is seeking a Lead Engineer/Staff for RISC-V Subsystem RTL Design in Bangalore. This role involves owning micro-architecture, RTL design, and integration for next-gen SoCs, collaborating with cross-functional teams, and debugging hardware issues.
Responsibilities
- Own micro-architecture, RTL design, integration, and delivery of RISC‑V subsystem components for next-generation SoCs.
- Work with architecture, software, verification, and SoC teams to define requirements, interfaces, memory maps, interrupt architecture, power features, and subsystem integration strategies.
- Develop scalable micro-architecture specifications optimized for performance, power, area, safety, and product-specific use cases.
- Implement high-quality RTL using Verilog/SystemVerilog and drive design convergence.
- Collaborate with firmware, verification, and integration teams to enable subsystem bring-up, feature validation, performance tuning, and seamless deployment.
- Debug and resolve functional, integration, timing, power, and silicon issues.
- Drive technical reviews, mentor junior engineers, contribute to subsystem roadmap planning, and coordinate execution.
Requirements
- Strong VLSI digital design experience with expertise in micro-architecture development and RTL implementation.
- Good understanding of RISC‑V architecture, interrupt handling, memory management concepts, power management, debug infrastructure, and system-level design principles.
- Knowledge of on-chip interconnect protocols such as AXI, AHB, APB, ACE, CHI, or equivalent high-performance SoC fabrics.
- Strong debugging, analytical, and problem-solving skills.
- Good understanding of ASIC development flow including architecture, RTL design, synthesis, timing closure, verification, and silicon bring-up.
- Effective communication and collaboration skills.
Desired Qualifications
- Experience with low-power design techniques including clock gating, power collapse, retention, isolation, voltage domains, and UPF-based design methodologies.
- Familiarity with interrupt architectures such as RISC‑V AIA/APLIC/IMSIC, system control processors, safety mechanisms, and subsystem infrastructure IPs.
- Proficiency in scripting languages such as Python, Perl, or Tcl for automation, flow development, and productivity improvements.
- Working knowledge of synthesis, DFT, CDC/RDC, formal verification, assertions, performance analysis, and system-level modeling.
Benefits
- Qualcomm is an equal opportunity employer.
- Qualcomm is committed to providing an accessible process for individuals with disabilities.
- Qualcomm is committed to making our workplace accessible for individuals with disabilities.
#RISC-V#RTL Design#SoC#VLSI#Hardware Engineering#ASIC#Micro-architecture
Company
Qualcomm
Job Posted
1 month ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Mid-Senior
Locations
Bangalore, India
Qualification
Bachelor, Master, Doctoral
Applicants
Be an early applicant