IP Verification- Staff Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Synopsys is looking for an ASIC Verification Staff Engineer in Bengaluru, Karnataka, India. The role involves designing and developing advanced verification environments for DesignWare IP cores using System Verilog and UVM/OVM/VMM. You will be responsible for test plans, test cases, functional coverage analysis, and collaborating with RTL designers. Familiarity with protocols like MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, and USB is required, along with scripting languages like Perl, TCL, and Python.

Responsibilities

Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies.
Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements.
Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities.
Perform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics.
Collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure.
Leverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity.
Contribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.

Requirements

BSEE with 5+ years or MSEE with 3+ years of relevant experience in ASIC or IP verification.
Expertise in developing HVL (System Verilog)-based verification environments and testbenches.
Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools.
Proficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable.
Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB.
Familiarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus.
Demonstrated ability to work with functional coverage-driven methodologies and quality metric goals.

Desired Qualifications

Analytical thinker with strong problem-solving and debugging skills.
Excellent verbal and written communication abilities.
Team player who thrives in collaborative, multi-site environments.
Proactive, self-motivated, and able to take initiative on challenging projects.
Detail-oriented, quality-focused, and driven by a desire to excel.
Adaptable and eager to continuously learn and apply new technologies.

Benefits

Comprehensive medical and healthcare plans.
ETO and FTO Programs.
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
ESPP with a 15% discount and a 24-month look-back.
Retirement plans.
Competitive salaries.

Skills

System VerilogUVMOVMVMMPerlTCLPythonMIPI-I3CUFSAMBAEthernetDDRPCIeUSBVerilogVCSNCMTI

#Engineering#ASIC#Verification#Staff Engineer#Semiconductor#Chip Design#IP Integration

About Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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