IC/FPGA Design Verification Engineer, Sr Staff

Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing

In short

Qualcomm is looking for a Sr Staff IC/FPGA Design Verification Engineer in Ottawa, Ontario. This role involves technical leadership for verification activities, architecting and developing verification environments using SystemVerilog and UVM, and driving verification closure for high-speed interconnect ASICs and FPGAs.

Responsibilities

Deliver standards-compliant IP blocks and subsystems for PCIe Gen7, CXL 4.0, UALink, Ethernet, and next-generation high-speed interconnect ASICs and FPGAs.
Provide technical leadership for verification activities across IP, subsystem, and system-level designs.
Architect, develop, and document scalable verification environments using SystemVerilog and UVM.
Develop comprehensive verification test plans and drive verification closure.
Develop, debug, and optimize complex test cases to achieve functional and coverage goals.
Drive bug tracking, root-cause analysis, and issue resolution from discovery through closure.
Improve engineering productivity through advanced tools, AI-driven verification techniques, automation, and scripting solutions.
Collaborate closely with architecture, design, software, validation, and customer teams to ensure successful product execution.
Mentor junior and senior engineers, promoting technical excellence and verification best practices across the organization.

Requirements

MSc/MEng with 7+ years of experience, or BSc/BEng with 10+ years of experience in ASIC or FPGA development and verification.
Deep knowledge of high-speed communication and interconnect protocols such as PCIe, CXL, UALink, and Ethernet.
Expert-level experience with SystemVerilog, UVM, constrained-random, and coverage-driven verification methodologies.
Strong understanding of IP, subsystem, and SoC-level verification.
Extensive experience with simulation, debugging, verification closure, functional coverage, and assertion-based verification.
Excellent technical leadership, communication, and problem-solving skills.
Ability to influence technical direction and drive alignment across cross-functional teams.

Desired Qualifications

Experience with PCIe Gen5/6/7 or CXL 3.0/4.0 from Physical Layer through Transaction Layer.
Experience with UALink and next-generation AI/HPC interconnect technologies.
Experience using PCIe/CXL VIPs from Siemens/Avery, Cadence, or Synopsys.
Experience leveraging AI-based approaches to improve verification productivity, test generation, debug, and coverage closure.
Experience with formal verification, emulation, or FPGA prototyping.
Experience defining or deploying verification methodologies used across multiple projects or teams.