CPU STA/Timing Engineer (Lead/Staff/Sr Staff)
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Qualcomm is seeking a CPU STA/Timing Engineer (Lead/Staff/Sr Staff) in Bangalore, India, to drive timing analysis and closure for high-performance CPU core and uncore designs. This role involves close collaboration with microarchitecture, RTL, DFT, and physical design teams to meet aggressive frequency and power targets across complex multi-GHz CPU designs.
Responsibilities
- Drive timing analysis and closure for complex, multi-GHz CPU designs across block, cluster, and full-chip hierarchies.
- Define, implement, and validate timing constraints in close collaboration with CPU microarchitecture, RTL, and DFT teams.
- Perform STA for high-performance CPU designs at block, cluster, and SoC/top-level hierarchies.
- Analyze timing on frequency-critical CPU paths and collaborate with RTL and DFT teams for logic and micro-architectural fixes.
- Provide actionable timing feedback to physical design engineers for CPU frequency and timing closure.
- Partner with CAD and methodology teams to develop and enhance CPU-specific timing flows.
- Generate and review timing ECOs to close setup, hold, noise, and cross-talk violations.
- Contribute to CPU timing methodology definition and best practices.
Requirements
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field and 2+ years of Hardware Engineering experience.
- OR Master's degree in Computer Science, Electrical/Electronics Engineering, or related field and 1+ year of Hardware Engineering experience.
- OR PhD in Computer Science, Electrical/Electronics Engineering, or related field.
- Strong experience with STA and timing closure for high-performance CPU or processor-class SoCs.
- Experience in multi-clock, multi-domain CPU designs with aggressive frequency targets.
- Proven experience performing STA on large CPU/SoC designs with multi-scenario and signoff-quality closure.
- Solid understanding of standard cell libraries, CPU-critical path optimization, and timing trade-offs.
- Excellent communication skills.
Desired Qualifications
- MS degree in Electrical Engineering with 3+ years of hands-on experience in STA and timing closure.
- Experience in deep sub-micron technology nodes and advanced process technologies.
- Hands-on knowledge of timing ECO techniques.
- Familiarity with circuit modeling, transistor fundamentals, and worst-case corner selection.
- Strong understanding of industry-standard synthesis, place & route, and tape-out flows.
- In-depth knowledge of timing effects such as noise, cross-talk, OCV/variation.
- Working knowledge of CPU/SoC architecture and HDL languages such as Verilog.
Benefits
- Opportunity to work on high-performance CPU core and uncore designs.
- Drive timing analysis and closure for complex, multi-GHz CPU designs.
- Collaborate with cross-functional teams including microarchitecture, RTL, DFT, physical design, and CAD.
#CPU#STA#Timing#Hardware Engineering#Physical Design#Microarchitecture#RTL
Company
Qualcomm
Job Posted
3 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bangalore, India
Qualification
Bachelor, Master, Doctoral
Applicants
Be an early applicant