Theme

Language

Global EN
Sweden ENSV
India EN

ASICS Design Verification Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing

In short

Qualcomm is seeking an ASICS Design Verification Engineer for their Vancouver or Markham office. This role involves pre-silicon test planning, testbench development using SystemVerilog-UVM, and formal verification to ensure the comprehensive verification of digital power IPs. The position requires a Bachelor's degree and 2+ years of experience in ASIC design and verification.

Responsibilities

  • Responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support.
  • Conduct comprehensive pre-silicon test planning for digital power IP's.
  • Develop testbench using advanced verification methodology such as SystemVerilog-UVM.
  • Develop coverage, assertion models, and perform formal verification (property checking).
  • Learn and deploy power-aware UPF verification flow and methodology.
  • Involve in developing automation to improve verification efficiency.

Requirements

  • Bachelor's degree in Engineering, Science, or a closely related field.
  • 2+ years of experience with ASIC design and verification tools, techniques, and methodology.
  • Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience OR PhD in Science, Engineering, or related field.

Desired Qualifications

  • Master’s degree in Computer Science, Electrical Engineer, Computer Engineering, or a closely related field.
  • 6+ years of experience with ASIC design and verification tools, techniques, and methodology.
  • 6+ years of experience with digital design concepts and RTL languages such as SystemVerilog or Verilog, or VHDL.
  • 6+ years of experience with computer architecture fundamentals, Object-oriented programming concepts and C or C++ programming skills.
  • 6+ years of experience with developing block-level testbench environment using SystemVerilog.
  • 6+ years of experience with verification methodologies through coursework or past experiences such as UVM or OVM and exposure to Assertion based Formal Verification.
  • 6+ years of experience with scripting/automation skills using either Perl or python.
  • Experience with AMBA Bus protocol (AXI/AHB/APB etc) is desirable.
  • Knowledge or experience with Assertion Based Formal Verification is desirable.

Benefits

  • Competitive annual discretionary bonus program.
  • Opportunity for annual RSU grants.
  • Highly competitive benefits package designed to support your success at work, at home, and at play.

Skills

SystemVerilogUVMPythonPerlVerilogVHDLC++CAXIAHBAPB
#ASICS#Design#Verification#Engineer#Power IP#Test Planning#Testbench Development#SystemVerilog-UVM#Coverage Development#Assertion Model Development#Formal Verification#Property Checking#Power-Aware UPF#Automation#Verification Efficiency#Digital Power IP#Pre-Silicon Test Planning#Silicon Support#RTL#Computer Architecture#Object-Oriented Programming#AMBA Bus Protocol#Formal Verification#Scripting#RSU Grants#Discretionary Bonus
Qualcomm Logo

About Qualcomm

Enabling a world where everyone and everything can be intelligently connected.

Enabling a world where everyone and everything can be intelligently connected.\n\n

Qualcomm Logo

Company

Qualcomm

Job Posted

2 weeks ago

Employment Type

Full Time

Work mode

On Site

Salary

US$108,000–158,000 / year

Experience Level

Mid-Senior

Locations

Vancouver, Canada

Markham, Canada

Qualification

Bachelor, Master, Doctoral

Applicants

Be an early applicant