ASIC Verification- Senior Staff Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing
In short
Synopsys is seeking an accomplished ASIC Verification Senior Staff Engineer in Bengaluru, India to design and develop advanced verification environments for DesignWare IP cores using System Verilog and UVM. This role involves developing test plans, debugging testbenches, and performing coverage analysis for next-generation connectivity protocols.
Responsibilities
- Specify, architect, and implement advanced verification environments for DesignWare IP cores using System Verilog and state-of-the-art methodologies.
- Develop and execute comprehensive test plans, ensuring coverage of unit-level and system-level requirements.
- Design, code, and debug testbenches, test cases, and functional coverage models to validate complex IP functionalities.
- Perform functional coverage analysis and manage regression testing to achieve and maintain required quality metrics.
- Collaborate closely with RTL designers and global verification teams to resolve issues and drive verification closure.
- Leverage scripting (Perl, TCL, Python) to automate verification flows, streamline processes, and enhance productivity.
- Contribute to the development and refinement of verification methodologies, including VIP development and formal verification approaches.
Requirements
- BSEE with 8 years or MSEE with 6+ years of relevant experience in ASIC or IP verification.
- Expertise in developing HVL (System Verilog)-based verification environments and testbenches.
- Strong hands-on experience with industry-standard simulators (VCS, NC, MTI) and debugging tools.
- Proficiency in verification methodologies such as UVM, OVM, or VMM; exposure to formal verification is highly desirable.
- Solid understanding of protocols such as MIPI-I3C/UFS/Unipro, AMBA, SD/eMMC, Ethernet, DDR, PCIe, USB.
- Familiarity with scripting languages (Perl, TCL, Python) and HDLs (Verilog); experience with VIP development is a plus.
- Demonstrated ability to work with functional coverage-driven methodologies and quality metric goals.
Desired Qualifications
- Analytical thinker with strong problem-solving and debugging skills.
- Excellent verbal and written communication abilities.
- Team player who thrives in collaborative, multi-site environments.
- Proactive, self-motivated, and able to take initiative on challenging projects.
- Detail-oriented, quality-focused, and driven by a desire to excel.
- Adaptable and eager to continuously learn and apply new technologies.
Benefits
- Comprehensive medical and healthcare plans.
- ETO and FTO Programs (Time Away).
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
- ESPP (Purchase Synopsys common stock at a 15% discount, with a 24 month look-back).
- Retirement Plans.
- Competitive salaries.
#ASIC#Verification#Engineer#Hardware#Semiconductor#IP Cores#System Verilog#UVM#Connectivity Protocols
Company
Synopsys Inc
Job Posted
3 days ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bengaluru, India
Qualification
Bachelor, Master
Applicants
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