ASIC Digital Design, Staff Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Synopsys is looking for a Staff Engineer to design and develop cutting-edge semiconductor solutions in Porto, Portugal. The role requires at least 3 years of experience in digital design, RTL development using Verilog/SystemVerilog, and a solid understanding of DFT, synthesis, timing, and power analysis.

Responsibilities

Design and implement RTL for digital and mixed signal IP blocks using Verilog and SystemVerilog.
Participate in architecture exploration and contribute to design specifications.
Run synthesis exploration, analyze timing and power results, and iterate on RTL to meet performance targets.
Support DFT and ATPG flows and coverage analysis.
Generate high-quality documents for customers and internal teams.
Collaborate with verification engineers to debug failures and close coverage gaps.
Integrate AI-assisted tools into the workflow to improve efficiency.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a closely related field.
At least 3 years of hands-on experience in ASIC digital design, RTL development, or front-end design flows.
Strong proficiency in Hard Description Languages (Verilog, SystemVerilog, VHDL).
Solid understanding of DFT and ATPG methodologies.
Experience with synthesis flow, constraints mapping, timing analysis, and power optimization.
Fluency in English, both written and spoken.

Desired Qualifications

Experience with high-speed memory interfaces such as DDR/HBM is a strong plus.
Ability to take an architecture discussion and turn it into a design spec.
Skill in debugging timing failures by analyzing RTL and critical paths.
Ability to catch issues in code review by considering downstream impacts.
Comfort working across time zones with a global team.
Pride in creating documentation that does not require constant clarification.

Benefits

Comprehensive medical and healthcare plans.
ETO and FTO Programs.
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
ESPP - Purchase Synopsys common stock at a 15% discount.
Retirement Plans.
Competitive salaries.

Skills

VerilogSystemVerilogVHDLDDRHBM

#ASIC#Digital Design#Staff Engineer#RTL#Verilog#SystemVerilog#VHDL#DFT#ATPG#Synthesis#Timing Analysis#Power Optimization#DDR#HBM

About Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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