Applications Engineer - ICV Runset Development
Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing
In short
Synopsys is looking for an experienced Applications Engineer to develop and validate DRC, LVS, and Fill runsets for IC Validator, focusing on advanced semiconductor process nodes. This role involves deep engagement with foundries and customers, requiring strong scripting skills in Perl, Tcl, and Python, and a solid understanding of physical verification and CMOS layouts. The ideal candidate will also mentor junior engineers and contribute to the product roadmap.
Responsibilities
- Develop and validate DRC, LVS, and Fill runsets for IC Validator, targeting advanced semiconductor process nodes from 7nm to 3nm and beyond.
- Work directly with foundry partners to translate process design kits and manufacturing requirements into production-ready rule decks.
- Automate runset qualification workflows using Perl, Tcl, and Python, reducing manual verification cycles and improving consistency across releases.
- Debug complex layout verification failures, including LVS topology mismatches, DRC false positives, and DFM rule interactions that block customer tapeouts.
- Interface with customers and field application engineers to gather requirements, reproduce issues, and deliver technical solutions that keep their projects on track.
- Mentor junior engineers on PV best practices, IC Validator capabilities, and effective debugging techniques.
- Track competitive EDA tools like Calibre and Pegasus, understanding their feature sets and how IC Validator differentiates in the market.
Requirements
- B.Tech, M.Tech, or MS in Electronics, VLSI, or related engineering discipline.
- 5-8 years of hands-on experience in Physical Verification, with a focus on DRC, LVS, and Fill rule deck development.
- Deep proficiency with IC Validator, Calibre, Pegasus, or PVS, with experience writing and debugging complex runsets in at least one of these tools.
- Strong scripting skills in Perl, Tcl, and Python for automating PV workflows and qualification processes.
- Solid understanding of CMOS transistor layouts, ASIC design flows, and how layout decisions impact manufacturability and yield.
- Experience working with foundry PDKs and translating process rules into executable verification decks.
- Familiarity with competitive EDA tools and the ability to articulate technical tradeoffs between different PV platforms.
Desired Qualifications
- Exposure to sub-10nm nodes is a strong plus.
- Ability to take a 500-page foundry design manual and turn it into a working DRC deck without needing extensive guidance.
- Systematic approach to debugging LVS run failures with numerous errors.
- Comfortable communicating with stressed customers before tapeout to resolve layout issues.
- Strong belief in and practice of mentoring junior engineers by explaining the 'why'.
- Genuine curiosity and desire to stay current on process technology and EDA tool developments.
- Ability to manage multiple projects, escalations, and qualification cycles simultaneously without losing track.
Benefits
- Comprehensive range of health, wellness, and financial benefits.
- Total rewards include both monetary and non-monetary offerings.
#semiconductor#VLSI#EDA
Company
Synopsys Inc
Job Posted
2 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Mid-Senior
Locations
Bengaluru, India
Qualification
Bachelor, Master
Applicants
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