Analog Design, Sr Staff Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Synopsys is looking for a Sr. Staff Engineer with extensive analog design experience, particularly in SerDes circuits, to develop cutting-edge semiconductor solutions. The role involves designing and optimizing analog front-end building blocks, running simulations, collaborating with layout and digital engineers, and owning the full lifecycle of blocks from spec to silicon for AI accelerators, data center switches, and automotive SoCs.
Responsibilities
- Design and optimize analog front-end building blocks for SerDes IP, including voltage and current-mode drivers, equalizers (CTLE, FFE, DFE), CDR circuits, PLLs, DLLs, VCOs, phase interpolators, bandgaps, and regulators.
- Run SPICE simulations across PVT corners and create verification test benches that validate performance against PCIe 6.0, PCIe 7.0, PAM4, Ethernet, USB, HDMI, or other high-speed protocol specifications.
- Collaborate closely with layout engineers to minimize parasitic resistance and capacitance, reduce mismatch, and account for proximity effects in sub-micron CMOS processes.
- Work with digital RTL engineers to verify calibration loops, adaptation algorithms, and control logic that tune analog circuits in real time.
- Present simulation results, design tradeoffs, and performance data in peer reviews and customer-facing technical discussions.
- Document circuit architecture, design features, verification strategies, and test plans for integration into larger SerDes products.
- Own the full lifecycle of blocks from spec to silicon, including post-layout verification, characterization support, and design-for-reliability checks for electromigration, IR drop, aging, and ESD.
Requirements
- PhD with 2+ years of hands-on SerDes or high-speed analog design experience, or BTech/MTech with 5 to 10 years in the same domain.
- Silicon-proven experience designing and bringing up analog or mixed-signal blocks in production chips.
- Deep expertise in at least several of these building blocks: analog front-end transceivers, voltage/current-mode drivers, PLLs, DLLs, VCOs, CDR circuits, bandgaps, regulators, CTLE, FFE, DFE, impedance calibrators, serializers, deserializers, or phase interpolators.
- Strong proficiency with SPICE simulation tools and sub-micron CMOS design methodologies.
- Experience optimizing layout for performance, including parasitic extraction, device matching, stress effects, and design-for-reliability considerations like electromigration, IR drop, and aging.
- Familiarity with scripting languages such as TCL or Perl for automation and simulation flow setup is a strong plus.
- Working knowledge of high-speed serial standards like PAM4, PCIe 6.0, PCIe 7.0, Ethernet, USB, SATA, HDMI, or MIPI is highly valued.
Desired Qualifications
- Ability to translate specification documents into circuit architectures independently.
- Proactive identification of layout issues and performance degradation in floorplan reviews.
- Comfortable presenting technical data to peers and customers.
- Willingness to challenge requirements or verification plans for accuracy.
- Effective cross-team collaboration with digital designers, layout engineers, and characterization engineers.
- Commitment to staying current on process technology and circuit techniques for improved designs.
Benefits
- Comprehensive medical and healthcare plans.
- ETO and FTO Programs in addition to company holidays.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Retirement plans that vary by region and country.
- Competitive salaries.
#semiconductor#hardware engineering#analog design#SerDes#IP#AI accelerators#data center switches#automotive SoCs#consumer electronics#PCIe 6.0#PCIe 7.0#PAM4#Ethernet#USB#HDMI