SOC Engineering, Senior Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Synopsys is hiring a Senior SOC Engineer in Sunnyvale, CA. This role involves designing and developing cutting-edge semiconductor solutions, including RTL coding, quality checks, and collaboration with cross-functional teams. The ideal candidate has a Bachelor's or Master's degree and 3-4 years of experience in ASIC/FPGA RTL design.
Responsibilities
- Write and review Verilog, SystemVerilog, or VHDL RTL for block-level designs including state machines, pipelines, FIFOs, and memory controllers based on micro-architecture specifications.
- Run RTL quality checks using tools like linting, CDC/RDC analysis, and synthesis to ensure your design is clean before handoff to physical design.
- Collaborate with verification engineers to debug testbench failures, refine corner cases, and close coverage gaps.
- Work with physical design teams to resolve timing issues, optimize logic for synthesis, and support timing closure from netlist through signoff.
- Implement standard interface protocols including AXI, APB, AHB, I2C, and SPI within SoC subsystems.
- Use scripting in Python, Tcl, or shell to automate repetitive tasks in the design flow and improve team productivity.
- Participate in design reviews with cross-functional teams across the globe, clearly communicating design decisions and tradeoffs.
Requirements
- Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
- 3 to 4 years of hands-on experience in ASIC or FPGA RTL design, implementation, and debug.
- Strong proficiency in Verilog, SystemVerilog, or VHDL RTL coding for registers, pipelines, state machines, memories, and FIFOs.
- Working knowledge of the ASIC design flow from micro-architecture through RTL development, synthesis, and timing closure.
- Experience using industry-standard tools such as simulators, lint checkers, CDC/RDC analysis tools, synthesis tools, and static timing analysis.
- Solid understanding of standard interface protocols including AXI, APB, AHB, I2C, and SPI.
Desired Qualifications
- Experience with more complex protocols like PCIe, DDR, or Ethernet is a plus.
- Familiarity with SystemVerilog assertions, C++, or Python for verification or scripting tasks.
- Experience with low-power design methodologies and UPF.
- Familiarity with DFT requirements.
- Experience with Git-based development flows.
- Familiarity with formal verification tools.
- Familiarity with AI-assisted engineering tools and code-generation assistants.
Benefits
- Comprehensive medical and healthcare plans.
- ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Retirement plans.
- Competitive salaries.
- Annual bonus, equity, and other discretionary bonuses.
- Comprehensive health, wellness, and financial benefits as part of a competitive total rewards package.
#SOC Engineering#Senior Engineer#RTL#ASIC#FPGA
Company
Synopsys Inc
Job Posted
21 hours ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Sunnyvale, United States
Qualification
Bachelor, Master
Applicants
Be an early applicant