The Job

Silicon Validation Engineer, Senior

Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing · Embedded Systems

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In short

Qualcomm is seeking a Senior Silicon Validation Engineer in Toronto, Ontario to characterize analog blocks, perform PHY/Link Layer/Protocol compliance, and bring up silicon. Responsibilities include defining test plans, developing scripts, automating test equipment, and studying signal/power integrity.

Responsibilities

  • Characterize analog blocks and perform PHY/Link Layer/Protocol compliance against various industry standards such as PCIe, Ethernet, and UCIe
  • Bring up silicon, debug issues, present test results, and generate validation reports
  • Define validation and regression test plans and develop test methodologies for various tests
  • Develop and standardize test scripts for various validation and regression tests that cover compliance and design features, and characterize chips over process, voltage, and temperature, and optimize firmware revisions
  • Determine equipment and accessories needs for various tests and automate test equipment
  • Study signal integrity and power integrity for evaluation boards and for silicon

Requirements

  • Bachelor's degree in Engineering Science, Electrical and Computer Engineering or Computer Science is at a minimum
  • Strong knowledge in various specifications such PCIe (Gen1 to Gen6), IEEE 100G CK (C2M, CR, KR), and OIF 100G CEI (VSR, MR, LR), 224G, UCIe, etc.
  • Strong programming skills in Python, Perl, Matlab, C/C++, HTML5 web languages or other scripting languages
  • Proficiency in using and automating test instruments such as Scope, BERT, Logic Analyzer/Exerciser, VNA, Power Supplies and Multimeters, etc.
  • Strong understandings of SerDes architecture (NRZ, PAM4) and theory of operation: PLL, CDR, CTLE, FFE, DFE, etc.
  • Experience in using compliance software such as SIGTEST, SEASIM, COM, etc.
  • Experience in PCB design and good understandings of signal integrity, insertion loss, return loss, TDR
  • Direct experience in SerDes related electrical validation

Desired Qualifications

  • Working experience with PCIe and Ethernet protocol layers is a definite plus
  • Good understanding of design blocks like MAC and PCS is a plus
  • Experience in optical and die2die validation is a plus
  • Experience in Mango Database, HTML, JavaScript, Numpy, SciPy, Seaborn, Matplotlib for data post processing and analysis is a plus
  • Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
  • PhD in Science, Engineering, or related field.

Benefits

  • Competitive annual discretionary bonus program
  • Opportunity for annual RSU grants
  • Highly competitive benefits package designed to support your success at work, at home, and at play
#Silicon Validation#ASIC Design#PHY/Link Layer#Protocol Compliance#PCIe#Ethernet#UCIe#Silicon Bring-up#Test Plans#Test Methodologies#Scripting#Signal Integrity#Power Integrity#SerDes Architecture#NRZ#PAM4#Compliance Software
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Company

Qualcomm

Job Posted

3 weeks ago

Employment Type

Full Time

WorkMode

Remote

Experience Level

Senior

Locations

Toronto, Canada

Qualification

Bachelor, Master, Doctoral

Applicants

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