Senior Technical Architect

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

We are seeking a Senior Technical Architect with 8 to 14 years of experience in ASIC/SoC verification for our Bangalore, India location. The role involves defining verification strategy, developing testplans and testbenches using UVM and SystemVerilog, and performing simulations and coverage analysis. Expertise in scripting languages and various protocols is also required.

Responsibilities

Define ASIC/SoC verification strategy.
Develop full chip testplans.
Define Full chip TB Architecture.
Develop UVM based testbench.
Develop TB components for SOC with C, SV.
Develop TB components, including functional coverage implementation and assertion coding.
Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics.
Debug complex simulation failures using waveform viewer tools.
Develop SOC C based tests coding & debugging.
Perform Gate level simulation & netlist debugging.
Analyze regression failures, Functional and Code Coverage closure.
Utilize scripting languages like Perl/Shell scripting to automate regression tests and parse large simulation log files.
Collaborate closely with the hardware design team to analyze, document, and resolve bug reports.
Document test plans, micro-architecture specifications, and verification results for team reviews.
ATE test

Requirements

8 to 14 years experience is mandatory.
Good understanding of ASIC/SoC life cycle.
Participated in multiple ASIC/SoC verification till tapeout stage.
Experience writing ASIC/SoC testplans.
Expertise & hands-on experience in OVM/UVM methodologies using SV.
Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.
Experience in developing TB components, including functional coverage implementation and assertion coding.
Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.
Experience in SOC C based tests coding & debugging.
Experience in Gate level simulation & netlist debugging.
Experience in regression failure analysis, Functional and Code Coverage closure.
Experience in Utilizing scripting languages like Perl/Shell scripting to automate regression tests and parse large simulation log files.
Proven industry experience in ASIC/SoC design and verification with multiple successful tape-outs.
Mastery of SystemVerilog, Verilog, and UVM (Universal Verification Methodology).
Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.
Expert proficiency with industry-leading EDA simulators, debuggers (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verd), and emulation platforms.
Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C, PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE).
Advanced capability in Python, Tcl, or Perl to create custom automation infrastructure for regressions and metrics tracking.
Ability to foresee technical risks weeks or months in advance and proactively implement mitigation strategies.
Strong leadership and communication skills to guide cross-functional teams and align stakeholders on technical directions.

Desired Qualifications

Strong understanding of CPU/GPU architectures, cache coherency, and memory controllers (e.g., DDR4/DDR5, HBM) is highly desirable.

Benefits

At HCLTech, you'll supercharge your potential. You'll find your career. And you'll find your spark.
All at a place that knows that helping its customers stay on top starts by putting its people first.
HCLTech is a global technology company, home to more than 230,000 people across 60 countries, delivering industry-leading capabilities centered around digital, engineering, cloud and AI, powered by a broad portfolio of technology services and products.
We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services.
Consolidated revenues as of 12 months ending September 2026 totaled $14.8 billion.

Skills

SystemVerilogVerilogUVMOVMCPythonPerlShell scriptingSVASPII2CPCIeNVMeEthernetUSBAMBA AXIAMBA CHIAMBA ACEDDR4DDR5HBMSynopsys VCSSiemens QuestaSimCadence XceliumVerdTcl

#ASIC/SoC verification#testplan development#testbench development#UVM#SystemVerilog#OVM#C#functional coverage#assertions coding#SVA#simulation#waveform viewer#gate level simulation#regression#coverage analysis#Perl#Shell scripting#hardware design#bug reports#Electronics & Communication Engineering#Electrical Engineering#VLSI Design#digital logic design#finite state machines#FIFO architectures#clocking concepts#CPU architectures#GPU architectures#cache coherency#memory controllers#EDA simulators#debuggers#emulation platforms#high-speed protocols#SPI#I2C#PCIe#NVMe#Ethernet#USB#AMBA AXI#AMBA CHI#AMBA ACE#Python#Tcl

About HCLTech

Supercharging progress through technology and innovation

HCLTech is a global technology company, home to 219,000+ people across 54 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending September 2022 totaled $12.1 billion. To learn how we can supercharge progress for…

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