Senior Technical Architect

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

We are seeking a Senior Technical Architect with 8-14 years of experience in ASIC/SoC verification, including full chip testplan development and UVM-based testbench development. The role involves defining verification strategy, ensuring functional coverage, and executing regressions. Requires expertise in SystemVerilog, Verilog, UVM, and scripting languages like Python or Perl.

Responsibilities

Define ASIC/SoC verification strategy.
Develop full chip testplans and participate in ASIC/SoC verification till tapeout.
Define full chip TB architecture.
Develop UVM-based testbenches using SystemVerilog.
Implement SV functional coverage and assertions.
Develop C-based TB components for SOC with C, SV.
Code, execute, and debug test cases.
Set up functional coverage, write system assertions, and analyze code coverage.
Debug complex simulation failures using waveform viewer tools.
Code and debug SOC C-based tests.
Perform Gate Level Simulation and netlist debugging.
Conduct regressions and coverage analysis, including failure analysis and closure.
Own and execute verification closure.
Utilize scripting languages like Perl/Shell scripting to automate regression tests and parse log files.
Collaborate with hardware design teams to resolve bug reports.
Document test plans, micro-architecture specifications, and verification results.

Requirements

8 to 14 years of experience.
Good understanding of ASIC/SoC life cycle.
Experience writing ASIC/SoC testplans.
Experience in ASIC/SoC Testbench definition.
Experience to Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and UVM.
Expertise & hands-on experience in OVM/UVM methodologies using SV.
Experience to Write, execute, and debug constrained-random and directed test cases based on defined test plans.
Experience in developing TB components for SOC with C, SV.
Experience in developing TB components, including functional coverage implementation and assertion coding.
Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics.
Experience in SOC C based tests coding & debugging.
Experience in Gate level simulation & netlist debugging.
Experience in regression failure analysis, Functional and Code Coverage closure.
Experience in Utilizing scripting languages like Perl/Shell scripting to automate regression tests and parse large simulation log files.
Experience in Collaborating closely with the hardware design team to analyze, document, and resolve bug reports efficiently.
Experience in Document test plans, micro-architecture specifications, and verification results for team reviews.
Proven industry experience in ASIC/SoC design and verification with multiple successful tape-outs.
Mastery of SystemVerilog, Verilog, and UVM (Universal Verification Methodology).
Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.
Expert proficiency with industry-leading EDA simulators, debuggers (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verd), and emulation platforms.
Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C, PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE).
Advanced capability in Python, Tcl, or Perl to create custom automation infrastructure for regressions and metrics tracking.
Ability to foresee technical risks weeks or months in advance and proactively implement mitigation strategies.
Strong leadership and communication skills to guide cross-functional teams and align stakeholders on technical directions.

Desired Qualifications

Strong understanding of CPU/GPU architectures, cache coherency, and memory controllers (e.g., DDR4/DDR5, HBM) is highly desirable.
Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), VLSI Design, or a closely related field.

Benefits

Consolidated revenues as of 12 months ending September 2026 totaled $14.8 billion.

Skills

SystemVerilogVerilogUVMOVMPythonPerlShell ScriptingTclAMBA AXIAMBA CHIAMBA ACESPII2CPCIeNVMeEthernetUSBDDR4DDR5HBMSynopsys VCSSiemens QuestaSimCadence XceliumCadence Verd

#ASIC#SoC#verification#testplan#UVM#SystemVerilog#OVM#Assertions#C#Gate Level Simulation#Regressions#Coverage Analysis#Scripting#Python#Perl#Shell#Tcl#Digital Logic#FSM#FIFO#CPU Architecture#GPU Architecture#Memory Controllers#Protocols#SPI#I2C#PCIe#NVMe#Ethernet#USB#AXI#CHI#ACE#EDA#Simulators#Debuggers#Emulation

About HCLTech

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HCLTech is a global technology company, home to 219,000+ people across 54 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending September 2022 totaled $12.1 billion. To learn how we can supercharge progress for…

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