Senior Physical Design Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Qualcomm is looking for a Senior Physical Design Engineer to own PNR implementation on the latest technology nodes for Qualcomm SoCs. The role requires expertise in Floorplanning, Placement, Clock Tree Synthesis (CTS), STA, and other signoff domains on Unix/Linux environments.
Responsibilities
- Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route, etc) on latest nodes.
- Signoff knowledge is mandatory (STA, Power analysis, FV, low power verification, PV, etc).
Requirements
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- OR PhD in Science, Engineering, or related field.
- 3+ years Hardware Engineering experience or related work experience.
- 3+ years' experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm).
Desired Qualifications
- PNR implementation for Qualcomm SoC's
- Good hands-on experience on Floorplanning, PNR and STA flows
- Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc
- Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc
- Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting
- Quick learner with good analytical and problem-solving skills
Benefits
- Qualcomm is an equal opportunity employer.
- Qualcomm is committed to providing an accessible process for individuals with disabilities.
- Qualcomm is committed to making our workplace accessible for individuals with disabilities.
#ASIC#PNR#STA#Floorplanning#Placement#Clock Tree Synthesis#Signoff#LEC#CLP#PDN