Senior Layout Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Qualcomm is looking for a Senior Layout Engineer in Bangalore, India, to develop chip layouts and floorplans. The role requires expertise in custom layout design, memory layout, automation scripting, and physical verification tools like Cadence and Calibre.

Responsibilities

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics.
Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs.
Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues.
Stays abreast of new verification methods.
Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.
Memory Leafcell layout library design from scratch including top level integration.
Proficient in SKILL and PERL for custom tiling and automations.
Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.
Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow.

Requirements

Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 2+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 4+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
High School diploma or equivalent and 6+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
2+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).
3-5 years of experience in Custom layout and Memory Layout design.
Good knowledge on different types of memory architectures and compilers.
Good knowledge in optimized layout design for better performance.
Sound knowledge & hands on experience in Finfet technology, DRC limitations and work closely with CAD engineers for better customization of DRC and tiling layout.

Desired Qualifications

Advanced degrees in a relevant field may be substituted for up to two years (Master’s = one year, Doctorate = two years) of the general custom layout design work experience in a relevant domain (e.g., analog, mixed signal, RF, digital design).

Benefits

Qualcomm is an equal opportunity employer.
Qualcomm is committed to providing an accessible process.
Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.
Qualcomm is also committed to making our workplace accessible for individuals with disabilities.

Skills

SKILLPERLCadenceLVSrmapCalibreDRCERC

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