In short
Join our Design Verification Methodology team as a Senior Engineer, shaping the next generation of Front-End CAD methodologies and EDA workflows for ASIC and FPGA development. This high-visibility role involves working with proprietary tools and exploring AI/ML applications in design automation. The position is based in Bangalore and requires significant experience in verification and scripting.
Responsibilities
- Lead the development, verification, deployment, and support of complex front-end DV tools / flows.
- Identify and solve flow, methodology, and tool inefficiencies across IP/ASIC/SoC environments; productize solutions to improve silicon quality and verification productivity.
- Drive innovation in design and verification processes, including AI-based enhancements.
- Collaborate closely with design, verification, test, and manufacturing teams to align on methodology, quality, and timelines.
- Troubleshoot technical challenges and implement scalable, long-term solutions.
- Foster a collaborative, forward-looking culture within the verification community.
Requirements
- Deep expertise in Testbench Architecture using SystemVerilog and UVM at IP, ASIC, and/or SoC level.
- Previous hands-on experience in scripting (Python, Perl, bash, csh, etc.).
- Strong knowledge of layered UVM environments, reusable testbench components, and block/subsystem/SoC-level verification strategies.
- Solid understanding of directed and constrained-random verification, SVA, functional and code coverage closure.
- Proficiency with front-end EDA tools: Verilog simulators, RTL/verification linters, CDC checkers, and formal verification.
- Experience with CI methodologies and tools (e.g., Jenkins).
- Strong grasp of modern silicon design methodologies and verification best practices.
- Experience collaborating across geographically distributed teams.
- Excellent communication skills and a strong sense of ownership in solving complex infrastructure challenges.
- BS/MS in Electrical Engineering, Computer Science, or related field.
- 10+ years of relevant experience in ASIC design verification.
Desired Qualifications
- Exposure to AI/ML applications in design and verification flows (e.g., testbench optimization, anomaly detection, coverage prediction) is a significant advantage.
Benefits
- Outstanding opportunity to use your skills and imagination to push the boundaries of what's possible.
- Build solutions never seen before to some of the world's toughest problems.
- Challenged, but not alone.
- Joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.
- Chance to work in a new Silicon R&D center in Bangalore.
- Opportunities for growth.
- Wealth of expertise to learn from.
- Potential to apply AI/ML techniques to silicon design and verification.
#ASIC#FPGA#Verification#Methodology#EDA#AI#ML#Design Automation#Frontend CAD
Company
Ericsson
Job Posted
3 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bangalore, India
Qualification
Bachelor, Master
Applicants
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