Senior Engineer - ASIC Backend
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Ericsson is seeking a Senior Engineer - ASIC Backend in Bangalore, India to work on the physical implementation of high-performance, low-power SoC designs. This role involves ownership of floorplanning, place-and-route, and timing closure, with support for synthesis and STA.
Responsibilities
- Own die-level and block-level floorplanning using Cadence Innovus or Synopsys ICC2.
- Plan and implement hierarchical design partitioning.
- Coordinate macro placement with memory compilers, analog IP, and hard macros.
- Design and implement the on-chip power delivery network.
- Execute full-chip and block-level placement and routing targeting timing, congestion, and power objectives.
- Perform clock tree synthesis (CTS).
- Manage routing for signal integrity.
- Drive iterative timing closure for setup and hold issues.
- Perform DRC, LVS, and ERC checks using Synopsys IC Validator or Cadence PVS.
- Develop and maintain PnR run scripts, methodology documentation, and automation flows in Tcl/Python.
Requirements
- B.Tech / M.Tech / M.S. in Electronics Engineering, VLSI Design, Computer Engineering, or a related field.
- 10+ years in physical implementation, floorplanning, or place-and-route roles.
- Expert-level proficiency with Cadence Innovus and/or Synopsys ICC2 / Fusion Compiler.
- Strong experience in die-level floorplanning, macro placement, and PDN design.
- Hands-on clock tree synthesis (CTS) experience across high-frequency, multi-clock designs.
- Expertise in timing-driven physical closure and ECO-based hold/setup fixing.
- Familiarity with physical verification tools (IC Validator, PVS) and DRC/LVS sign-off.
- Working knowledge of synthesis (Fusion Compiler) and STA (PrimeTime).
- Proficiency in Tcl; Python scripting a strong plus.
- At least one tape-out on 7nm or below.
Desired Qualifications
- Experience with low-power physical implementation (UPF/CPF, power domain crossings, multi-Vt strategies).
- Knowledge of advanced routing constraints — signal integrity shielding, differential pair routing, antenna fixing.
- DFT physical implementation experience — scan chain reordering, BIST placement, and test-mode timing closure.
- Exposure to formal equivalence checking (Formality, Conformal) post-ECO.
Benefits
- Opportunities to advance your skills.
- Supportive, innovative environment focused on quality, teamwork, and career development.
- Work on game-changing 5G/6G technologies.
#5G#6G#Telecom#SoC#ASIC#Physical Design#Floorplanning#Place and Route#Timing Closure#PDN#CTS#DRC#LVS#STA
Company
Ericsson
Job Posted
6 days ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bangalore, India
Qualification
Bachelor, Master
Applicants
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