Senior Designer

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

We are seeking a Senior Designer to analyze, model, and validate the timing and power characteristics of embedded memory/IPs. This role involves ensuring high-performance and low-power solutions across various corners using EDA tools and scripting.

Responsibilities

Perform timing characterization (setup/hold, access time, cycle time, pulse widths) for memory IPs.
Generate and validate timing models (.lib, CCS) across all corners (PVT variations).
Perform path analysis and debugging for timing failures.
Support STA teams with accurate timing models and insights.
Perform dynamic and leakage power characterization.
Generate power models (.lib) including internal, switching, and standby/leakage power.
Analyze low-power modes (retention, sleep, deep-sleep, DVFS scenarios).
Setup and maintain characterization environments using EDA tools (Cadence Liberate, Synopsys SiliconSmart).
Develop and maintain automation scripts (Python, Perl, Shell) for flow optimization.
Work on SPICE simulations (HSPICE, Spectre, XA) for accurate results.
Ensure accuracy and consistency of generated .lib models.
Validate model correlation with SPICE/golden simulations.
Debug characterization issues such as convergence failures, waveform inconsistencies, and model mismatches.

Requirements

Strong understanding of digital timing fundamentals (setup, hold, skew, slack).
Strong understanding of memory architecture (SRAM basics).
Experience in timing & power characterization tools (Synopsys SiliconSmart, Cadence Liberate / Liberate MX).
Experience in SPICE simulators (HSPICE, Spectre, XA).
Knowledge of PVT corners, OCV, derating, variation.
Familiarity with Liberty format (.lib), CCS models.
Understanding of low-power design techniques.
Proficiency in Python / Perl / Shell scripting.
Experience in automation and flow development.
3-5 Years hands-on execution of characterization runs.
3-5 Years basic debugging of tool/setup issues.
3-5 Years familiarity with .lib generation and validation.

Desired Qualifications

Silicon correlation & post-silicon debug experience.
Knowledge of advanced nodes (7nm, 5nm, below).
Familiarity with EM/IR, reliability, aging analysis.
Experience with memory compiler flows.

Benefits

Supercharge your potential at HCLTech.
Find your career at HCLTech.
Find your spark at HCLTech.
HCLTech knows that helping its customers stay on top starts by putting its people first.

Skills

SRAMPythonPerlShell scriptingCadence LiberateSynopsys SiliconSmartHSPICESpectreXALiberty formatCCS models

#Memory Timing#Power Characterization#Embedded Memory#SRAM#NVM#PVT Corners#Timing Models#Power Models#Low-power#EDA Tools#Automation Scripts#SPICE Simulations#Digital Timing#Memory Architecture#Scripting#Advanced Nodes#Silicon Correlation

About HCLTech

Supercharging progress through technology and innovation

HCLTech is a global technology company, home to 219,000+ people across 54 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending September 2022 totaled $12.1 billion. To learn how we can supercharge progress for…

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