Senior Design Lead

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

A Senior Design Lead role in Bangalore, Karnataka requiring 5-7 years of experience in ASIC/SoC verification, including testplan creation, UVM testbench development, and functional coverage. The position also involves C-based testbench development, gate-level simulation, regression analysis, and closure participation, utilizing scripting languages like Perl and Shell.

Responsibilities

Define ASIC/SoC testbench architecture.
Develop and maintain reusable block-level and sub-system testbenches using SystemVerilog and UVM.
Write, execute, and debug constrained-random and directed test cases.
Develop TB components for SOC with C and SV.
Implement functional coverage and assertions (SVA).
Analyze code coverage metrics to identify untested gaps.
Debug complex simulation failures using waveform viewer tools.
Code and debug SOC C-based tests.
Perform gate-level simulation and netlist debugging.
Analyze regression failures and achieve functional and code coverage closure.
Participate in verification closure.
Utilize Perl/Shell scripting for automation.

Requirements

5 to 7 years of experience is mandatory.
Good understanding of ASIC/SoC life cycle.
Participation in multiple ASIC/SoC verifications till tapeout stage.
Experience in ASIC/SoC Testbench definition.
Expertise & hands-on experience in OVM/UVM methodologies using SV.
Experience in developing TB components, including functional coverage implementation and assertion coding.
Experience setting up functional coverage, writing system assertions (SVA), and analyzing code coverage metrics.
Experience in debugging complex simulation failures.
Experience in SOC C based tests coding & debugging.
Experience in Gate level simulation & netlist debugging.
Experience in regression failure analysis.
Proficiency in Verilog, SystemVerilog, and core concepts of UVM.
Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.
Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verdi).
Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C, PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE).
Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for automation.

Desired Qualifications

Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), VLSI Design, or a closely related field.

Skills

SystemVerilogUVMVerilogPerlShell scriptingPythonTclASICSoCSPII2CPCIeNVMeEthernetUSBAXICHIACE

#ASIC#SoC#verification#tapeout#testbench#UVM#SystemVerilog#assertions#C#debug#simulation#regressions#coverage#Perl#Shell#Verilog#digital logic#FSM#FIFO#clocking#VCS#QuestaSim#Xcelium#Verdi#SPI#I2C#PCIe#NVMe#Ethernet#USB#AXI#CHI#ACE

About HCLTech

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HCLTech is a global technology company, home to 219,000+ people across 54 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending September 2022 totaled $12.1 billion. To learn how we can supercharge progress for…

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