Senior Circuit Design Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Microsoft is looking for a Senior Circuit Design Engineer to join the Silicon, Cloud Hardware, and Infrastructure Engineering team. This role involves developing memory solutions for PPA challenges, working with process technologies, and devising methodologies for statistical analysis and characterization, contributing to the core infrastructure powering Microsoft's cloud businesses.
Responsibilities
- Collaborate with SoC designers to develop Memory SRAM and Register file solutions to difficult PPA challenges.
- Work with internal and external process technology teams to understand and exploit advanced process DTCO knobs.
- Devise methodologies for statistical analysis and timing/power/EMIR characterization.
- Run quality assurance checks on IP collateral.
- Develop IP and post-silicon characterization plans for inclusion on advanced process technology testchips.
- Develop scripting automation for flows.
Requirements
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
- Ability to meet Microsoft, customer and/or government security screening requirements.
- Pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
- Provide proof of country of citizenship or proof of U.S. permanent residency or other protected status for assessment of eligibility to access export-controlled information.
- Successfully verify citizenship with a valid passport, or for lawful permanent residents, refugees, and asylees, use other applicable documents.
Desired Qualifications
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience.
- 5+ years of experience in SRAM or Register file design.
- 5+ years of experience in timing, power, EMIR characterization.
- Experience in SRAM and Register File design in advanced process technologies.
- Understanding of SRAM write and read assist techniques.
- Understanding of process technology and DTCO.
- Understanding of layout and provide guidance to layout design.
- Experience in yield and reliability.
- Experience in providing technical guidance to other engineers and multitasking across multiple SoC programs.
- Ability to concisely communicate design value propositions and risks.
- Effective debug skills.
Benefits
- The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year.
- In the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is USD $160,200 - $261,000 per year.
- Certain roles may be eligible for benefits and other compensation.
#Azure#SCHIE#Silicon Engineering#Hardware Engineering#Circuit Design#SRAM#Register File#PPA#DTCO#Characterization#IP Collateral#Post-Silicon#Testchips#Automation
Company
Microsoft
Job Posted
3 weeks ago
Employment Type
Full Time
WorkMode
Hybrid
Experience Level
Senior
Locations
United States
Qualification
Doctoral, Master, Bachelor
Applicants
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