Principal Engineer, Silicon Engineering II

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

As a Principal Engineer, you will be the primary technical leader for chipset engineering planning and execution from early product definition through launch. This role involves driving end-to-end technical execution across a global, matrixed workforce to ensure custom hardware innovations are optimized and launched on schedule. The position requires extensive experience in custom silicon design, SoC/ASIC implementation, and technical leadership, with a focus on delivering efficient chipset solutions.

Responsibilities

Direct the execution of the entire SoC lifecycle, from initial chip definition and top-level architecture through tape-out, silicon bring-up, and final mass production.
Partner with specialized teams to lead the integration of the proprietary gCPU and high-performance custom IPs, optimizing physical design layout to maximize hardware efficiency.
Collaborate with DSPG Silicon, Software, and Pixel Hardware teams to drive a "one team" model, ensuring hardware innovations have day-one software sponsorship and land seamlessly in production.
Coordinate deliverables across a highly matrixed global workforce, aligning schedules, managing dependencies, and actively resolving complex technical blockers.
Lead critical debug forums to drive complex system failure signatures to rapid root-cause closure by driving actions across all teams.

Requirements

Bachelor's degree in Electrical Engineering, Computer Science, or a related field, or equivalent practical experience.
15 years of experience with custom silicon design, SoC/ASIC implementation, or hardware-software co-design.
10 years of experience in technical leadership.
Experience directing SoC development programs from concept to mass production.

Desired Qualifications

Master's degree or PhD in Electrical Engineering, Computer Science, or a related field.
Experience managing global, cross-functional engineering deliverables and aligning schedules/dependencies across matrixed organizations.
Demonstrated change-management and operational leadership skills, with experience coordinating teams across global sites.
Expertise in driving complex hardware and software system-level debug and root-cause analysis.
Deep technical understanding of custom IP integration, physical design flows, and hardware-software co-design principles.

Benefits

US: $275000 - $382000 (USD) + 30% bonus target + equity + benefits
Learn more about benefits at Google.

Skills

SoCASIChardware-software co-designCPUIP integrationphysical design

#silicon engineering#chipset#hardware#software#engineering#technical leadership#SoC#ASIC#hardware-software co-design#electrical engineering#computer science#product definition#architecture#physical implementation#production#debug#root-cause analysis#IP integration#physical design#system-level

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