Physical Design Engineer, Senior Lead
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Qualcomm is seeking a Senior Lead Physical Design Engineer for their Hardware Engineering group in Hyderabad, India. This role involves planning, designing, and optimizing ASIC designs, with a focus on the Place and Route flow and methodology. The ideal candidate will have extensive experience in physical design, PNR, CTS, and sign-off checks.
Responsibilities
- Plan, design, optimize, verify, and test electronic systems, circuits, digital/analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.
- Execute complete PD ownership from netlist to GDS2 including HM level PV, LEC, low-power checks and PDN, STA closure.
- Implement Voltage Islands and low power methodologies, flows and implementation.
- Debug Congestion and CTS issues.
- Understand and implement improving existing methodologies and flows.
- Effectively communicate the status and issues of respective owned Tasks.
- Work in a global team environment.
Requirements
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
- Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
- PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
- Thorough knowledge of the ASIC designs Place and Route flow and methodology.
- Hands-on experience in executing complete PD ownership from netlist to GDS2 including HM level PV, LEC, low-power checks and PDN, STA closure.
- Hands-on experience in Voltage Islands and low power methodologies, flows and implementation.
- Strong background in debugging Congestion and CTS issues.
- Expertise in PnR tools (Innovus/Fusion compiler) and flow.
- Familiarity with Sign-off(PV/PDN/STA/FV/CLP/Scan-DRC(tk)) methodology and tools.
- Proficient in scripting languages (TCL,PERL,PYTHON).
- 4-10 years of experience in physical design including floorplanning, PNR, CTS and signoff checks.
Desired Qualifications
- Self-starter and highly motivated.
Benefits
- Qualcomm is an equal opportunity employer.
- Qualcomm is committed to providing an accessible process for individuals with disabilities.
- Qualcomm is committed to making our workplace accessible for individuals with disabilities.
Skills
ASIC DesignPlace and RouteGDS2PVLEClow-powerPDNSTAVoltage IslandsCongestionCTSInnovusFusion CompilerSign-offTCLPERLPYTHON
#Hardware Engineering#ASIC#Physical Design#Place and Route#Sign-off
About Qualcomm
Enabling a world where everyone and everything can be intelligently connected.
Enabling a world where everyone and everything can be intelligently connected.\n\n
Company
QualcommJob Posted
2 weeks ago
Employment Type
Full Time
Work mode
On Site
Experience Level
Senior
Locations
Hyderabad, India
Qualification
Bachelor
Applicants
Be an early applicant
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