Physical Design Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Qualcomm sucht erfahrene Physical Design Engineers zur Verstärkung der SoC- und ASIC-Designorganisation. Die Rolle umfasst alle Phasen des Physical Design Flows auf fortschrittlichen Prozesstechnologien, mit Fokus auf Hochleistungsrechnen, KI, Mobil- und Automobilanwendungen. Erfolgreiche Kandidaten werden an der Entwicklung von ASICs und SoCs mitarbeiten, einschließlich Floorplanning, Timing-Analyse und Low-Power-Implementierung.
Responsibilities
- Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
- Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs.
- Perform floorplanning, partitioning, power planning, and IR-drop analysis.
- Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios.
- Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
- Perform RC extraction, physical verification, and formal verification activities.
- Implement engineering change orders (ECOs) and support design convergence through sign-off.
- Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful project execution.
- Contribute to the development of innovative low-power implementation methodologies and customized place-and-route solutions.
- Develop automation and productivity tools using scripting languages and software development techniques.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- 2-10+ years of industry experience or relevant academic/project experience in Physical Design.
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Desired Qualifications
- Experience in one or more of the following areas: ASIC/SoC Physical Design implementation.
- Place and Route using Cadence Innovus and/or Synopsys Fusion Compiler.
- Static Timing Analysis and timing closure using Synopsys PrimeTime SI.
- Physical verification and design sign-off methodologies.
- Formal verification techniques and tools.
- Power domain implementation and low-power design methodologies.
- Clock Tree Synthesis (CTS), routing, and timing optimization.
- Low power implementation techniques experience.
- Signal integrity, noise analysis, and MMMC sign-off flows.
- DFT-aware physical implementation and constraint management.
- Programming and automation using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments.
- Perl/Tcl, Python skills are needed.
- Strong problem solving and ASIC development/debugging skills.
Benefits
- Competitive annual discretionary bonus program.
- Opportunity for annual RSU grants.
- Highly competitive benefits package designed to support your success at work, at home, and at play.
Skills
Cadence InnovusSynopsys Fusion CompilerSynopsys PrimeTime SIPythonPerlTCLShell scriptingC++LinuxUnix
#ASIC#SoC#Physical Design#Engineering#Electrical Engineering#Computer Engineering#Computer Science#Semiconductor#AI#Mobile#Automotive#Data Center
About Qualcomm
Enabling a world where everyone and everything can be intelligently connected.
Enabling a world where everyone and everything can be intelligently connected.\n\n
Company
QualcommJob Posted
3 days ago
Employment Type
Full Time
Work mode
On Site
Salary
US$145,600–218,400 / year
Experience Level
Mid-Senior
Locations
Austin, United States of America
Qualification
Bachelor, Master, Doctoral
Applicants
Be an early applicant
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