Physical Design Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Qualcomm is seeking a Physical Design Engineer to define, model, design, optimize, and implement IP for next-generation products. The role requires hands-on experience with PNR and STA flows, including floorplanning, placement, CTS, and signoff domains. A Bachelor's degree and 2+ years of relevant experience are required.
Responsibilities
- Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes.
- Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc)
- PNR implementation for Qualcomm SoC's
- Define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products.
Requirements
- Bachelor's degree in Science, Engineering, or related field.
- 2+ years Hardware Engineering experience or related work experience.
- 2+ years' experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm)
- Good hands-on experience on Floorplanning, PNR and STA flows
- Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc
- Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc
- Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting
- Quick learner with good analytical and problem-solving skills
#ASIC#Physical Design#PNR#STA#Floorplanning#CTS#Signoff#LEC#CLP#PDN#Unix#Linux#Perl#TCL