Physical Design Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Qualcomm is seeking Physical Design Engineers to join their SoC and ASIC Design organization. This role involves contributing to various projects, including high-performance computing, AI, and mobile technologies, with opportunities to work on different aspects of Physical Design ASIC and SoC development.
Successful candidates will execute and drive all stages of the physical design flow, from synthesized netlist to tape-out, and collaborate with cross-functional teams to ensure successful project execution.
Responsibilities
- Execute and drive all stages of the physical design flow from synthesized netlist to tape-out.
- Develop and implement physical design solutions for complex, high-speed, and low-power ASICs and SoCs.
- Perform floorplanning, partitioning, power planning, and IR-drop analysis.
- Execute placement, clock tree synthesis (CTS), routing, timing optimization, and timing closure across Multi-Mode Multi-Corner (MMMC) scenarios.
- Analyze and resolve timing violations, signal integrity issues, crosstalk effects, and physical design rule violations.
- Perform RC extraction, physical verification, and formal verification activities.
- Implement engineering change orders (ECOs) and support design convergence through sign-off.
- Collaborate with architecture, RTL, DFT, verification, and methodology teams to ensure successful project execution.
- Contribute to the development of innovative low-power implementation methodologies and customized place-and-route solutions.
- Develop automation and productivity tools using scripting languages and software development techniques.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- 2-10+ years of industry experience or relevant academic/project experience in Physical Design.
- ASIC/SoC Physical Design implementation.
- Place and Route using Cadence Innovus and/or Synopsys Fusion Compiler.
- Static Timing Analysis and timing closure using Synopsys PrimeTime SI.
- Physical verification and design sign-off methodologies.
- Formal verification techniques and tools.
- Power domain implementation and low-power design methodologies.
- Clock Tree Synthesis (CTS), routing, and timing optimization.
- Low power implementation techniques experience
- Signal integrity, noise analysis, and MMMC sign-off flows.
- DFT-aware physical implementation and constraint management.
- Programming and automation using Python, Perl, TCL, Shell scripting, C/C++, and Linux/Unix environments.
- Perl/Tcl, Python skills are needed.
- Strong problem solving and ASIC development/debugging skills.
Benefits
- Competitive annual discretionary bonus program
- Opportunity for annual RSU grants
- Highly competitive benefits package designed to support your success at work, at home, and at play.
Skills
PythonPerlTCLShell scriptingC++LinuxUnixCadence InnovusSynopsys Fusion CompilerSynopsys PrimeTime SI
#ASIC#SoC#Physical Design#low power#timing analysis#tape-out#floorplan#Clock Tree Synthesis#IR-drop analysis#placement#routing#timing optimization#physical verification#formal verification#ECO#automation#scripting
About Qualcomm
Enabling a world where everyone and everything can be intelligently connected.
Enabling a world where everyone and everything can be intelligently connected.\n\n
Company
QualcommJob Posted
2 days ago
Employment Type
Full Time
Work mode
On Site
Salary
US$159,600–239,400 / year
Experience Level
Mid-Senior
Locations
Santa Clara, United States of America
Qualification
Bachelor, Master
Applicants
Be an early applicant