Performance Optimization Architect/Manager

Technology, Data & Digital · IT Infrastructure & Security · Systems Engineering · Software Engineering

In short

Qualcomm seeks a Performance Optimization Architect/Manager in Bangalore, India, to analyze and optimize complex GPU and SoC performance. This role involves in-depth performance analysis, bottleneck identification, and collaboration with architecture teams to define next-generation Adreno GPUs. The ideal candidate will possess a strong background in computer graphics, system-on-chip architecture, and relevant programming/scripting languages.

Responsibilities

Conduct system-level performance analysis and bottleneck analysis for high-performance GPUs and SoCs.
Utilize hardware models (performance models, RTL test benches, emulators, silicon) to identify performance bottlenecks.
Understand key product use-cases and formulate test suits for graphics, machine learning, automotive, video, and computer vision.
Collaborate with architecture and design teams on system performance, area, and power trade-offs.
Develop infrastructure including performance models, testbench components, and analysis tools.
Lead efforts to enhance turnaround time, identify representative data-sets, and facilitate early performance analysis.

Requirements

Bachelor’s (BE/BTech) or Master’s (MS/MTech) degree in a relevant field; PhD is a plus, or equivalent experience.
Minimum of 12 years of experience in Computer Graphics or a related field with exposure to performance analysis and complex System-on-Chip (SoC) and/or GPU architectures.
Profound understanding of System-on-Chip (SoC) architecture, graphics pipeline, memory subsystem architecture, and Network-on-Chip (NoC)/Interconnect architecture.
Expertise in programming languages (C/C++) and scripting languages (Perl/Python).
Strong debugging and analysis skills, including data and statistical analysis, and proficiency in using RTL dumps to debug failures.
Knowledge of Graphics APIs e.g. OpenGL, Vulkan, DirectX, Metal.

Desired Qualifications

Exposure to Verilog/System Verilog, SystemC/TLM is highly advantageous.
Hands-on experience in developing performance simulators and cycle accurate/approximate models for pre-silicon performance analysis is a significant advantage.
Experience with benchmark analysis, 3D graphics, and compiler technologies.