Performance Modeling Engineer Processor, AI Accelerator, and SoC Architecture- Sr.Staff

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Qualcomm is looking for a Senior Staff Performance Modeling Engineer to focus on next-generation processors, AI accelerators, and SoC platforms. This role involves developing high-fidelity performance models, evaluating architectural tradeoffs, and guiding design decisions with expertise in processor architecture, memory systems, and TLM.

Responsibilities

Develop and maintain transaction-level and analytical performance models for processors, memory hierarchies, interconnects, and accelerators.
Create detailed models of cache hierarchies, coherent interconnects, memory subsystems, DMA engines, and SMP systems.
Evaluate architectural tradeoffs involving performance, power, area, latency, bandwidth, and scalability.
Analyze workload behavior and identify system bottlenecks through simulation and modeling.
Drive architectural studies for next-generation multicore and cache-coherent systems.
Perform deep performance analysis of branch prediction, hardware prefetching, speculative execution, load/store architectures, cache coherence protocols, and memory consistency models.
Model and validate the behavior of multithreaded and multiprocessor workloads.
Collaborate with hardware and software teams to correlate performance models with RTL simulations, emulation results, and silicon data.
Present architectural recommendations and performance insights to engineering leadership.

Requirements

BS, MS, or PhD in Computer Engineering, Electrical Engineering, Computer Science, or related field.
10+ years of industry experience in computer architecture, microarchitecture, or performance modeling.
Strong understanding of processor architecture and microarchitecture, cache and memory hierarchy design, SMP systems, and multicore scaling challenges.
Experience developing Transaction-Level Models (TLM/SystemC), analytical performance models, and architectural simulators.
Deep knowledge of cache behavior, including capacity and conflict effects, latency analysis, prefetching techniques, memory locality, and coherence interactions.
Familiarity with modern cache coherence protocols such as ARM CHI, ACE, and MESI/MOESI-based protocols.
Strong understanding of memory consistency models, atomic operations, synchronization mechanisms, and ordering semantics.
Strong software development skills in C++, Python, or equivalent languages.

Desired Qualifications

Experience modeling AI accelerators, CPUs, GPUs, or heterogeneous compute architectures.
Understanding of Network-on-Chip (NoC) architectures, memory controllers, DDR and HBM memory systems, and virtualization technologies such as SR-IOV.
Familiarity with formal verification methods for cache coherence and memory ordering.
Experience correlating pre-silicon performance models with silicon measurements and performance counters.
Knowledge of power-performance analysis and optimization techniques.

Benefits

Competitive annual discretionary bonus program.
Opportunity for annual RSU grants.
Highly competitive benefits package designed to support success at work, at home, and at play.

Skills

C++PythonSystemC

#Processor Architecture#AI Accelerator#SoC Architecture#Performance Modeling#System-Level Optimization#Memory Systems#Cache Hierarchies#Transaction-Level Modeling#RTL#Verification#Software#System Teams#Microprocessor Design#DMA Engines#Multiprocessor Systems#Cache Coherence#ARM CHI#ACE#MESI/MOESI#Memory Consistency Models#Atomic Operations#Synchronization Mechanisms#Ordering Semantics#Network-on-Chip#Memory Controllers#HBM#Virtualization#Formal Verification#Silicon Measurements#Performance Counters#Power-Performance Analysis#C++#Python#SystemC