Lead Layout Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Develops block, macro, or chip level layouts and floorplans according to project requirements. Creates accurate designs meeting project needs, troubleshoots issues using various tools, and collaborates with stakeholders. Requires experience in layout design and verification tools, Power Management modules, and physical verification using the Calibre Verification suite.

Responsibilities

Develops block, macro, or chip level layouts and floorplans according to project requirements, specifications, and design schematics.
Applies understanding of design manuals, established processes, layout elements, and basic electronic principles to create accurate designs that meet project needs.
Conducts analyses, tests, and verifies designs using different tools and techniques to identify and troubleshoot issues, and stays abreast of new verification methods.
Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.
Hands-on experience on various Power Management (PMIC) Module layouts.
Physical verification using Calibre Verification suite.
Extensive floor planning and signal planning skills in Cadence Virtuoso IC201 and above.
Layout Design for various analog circuits like: Linear and Switching Regulators, ADCs, DACs, CHARGERS, Envelope Trackers, APTs, High Current POWERFETS, OTAs, Error Amplifiers, etc.
Create area and parasitic efficient layouts, with strong problem-solving skills.
Create technical documentation and presentations.

Requirements

Bachelor's degree in Electrical Engineering, Computer Science, Mathematics, Electronic Engineering, or related field and 3+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
OR Associate's degree in Computer Science, Mathematics, Electrical Engineering or related field and 5+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
OR High School diploma or equivalent and 7+ years of experience designing custom layouts in relevant domain (e.g., analog, mixed signal, RF, digital design), or related work experience.
3+ years of experience using layout design and verification tools (e.g., cadence, LVS, rmap).
Completed advanced degrees in a relevant field may be substituted for up to two years (Master’s = one year, Doctorate = two years) of the general custom layout design work experience in a relevant domain (e.g., analog, mixed signal, RF, digital design).
Strong understanding of submicron, deep-submicron, High Voltage CMOS processes.
Very strong analog layout fundamentals and basic electrical knowledge for layout development.
Strong physical verification debugging capability using Calibre Verification Suite.
Ability to perform in a dynamic, team-oriented environment.
Well-developed organizational skills and the ability to multi-task.
Strong communication skills for efficient delivery.
Team player skills to work with geographically spread team members.

Desired Qualifications

SOI process knowledge is an advantage.
Scripting knowledge in SKILL/PERL/SHELL and hands on knowledge of AI based layout development flow is an advantage.
Graduation in Electrical or Electronics is preferred with 5+ years of exp.
Diploma with minimum 8 years of hands on layout development experience is also okay.

Benefits

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process.
Qualcomm is also committed to making our workplace accessible for individuals with disabilities.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Skills

Cadence VirtuosoLVSCalibre Verification SuiteSKILLPERLSHELLanalog circuitsPower ManagementCMOSSOIelectronic engineeringCommunication EngineeringCircuits

#layout design#floor planning#analog circuits#switching regulators#ADCs#DACs#chargers#high current#power FETs#OTAs#error amplifiers#CMOS#SOI#physical verification#Calibre#Cadence Virtuoso#SKILL#PERL#SHELL