ISP Design Engineer, up to Staff
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Qualcomm is seeking a seasoned ISP Design Engineer in Taipei to architect and develop advanced Image Signal Processing (ISP) hardware pipelines for high-performance, low-power semiconductor products. This role involves defining micro-architectures, building models, implementing hardware, optimizing PPA, and validating ISP functions, requiring strong depth in imaging algorithms and practical hardware execution.
Responsibilities
- Architect, design, and optimize ISP hardware modules including demosaic, noise reduction, color correction, tone mapping, sharpening, HDR merging, spatial/temporal filtering, and other image quality pipelines.
- Translate imaging specifications and algorithm requirements into efficient micro architecture and hardware friendly implementations, balancing image quality with area, power, and latency constraints.
- Develop C/C++/SystemC models for algorithm validation, performance estimation, bandwidth analysis, and design space exploration.
- Evaluate ISP performance using KPIs such as image quality metrics, throughput, latency, memory bandwidth, and power efficiency; propose design enhancements based on quantitative data.
- Collaborate with verification teams to define test plans, reference model comparisons, coverage metrics, and debugging flows for robust pre silicon validation.
- Work with PD teams to meet PPA targets via pipeline design, timing closure strategies, clock/power domain planning, and architecture trade off analyses.
- Support post silicon bring up, tuning, debugging, and performance correlation against pre silicon models.
- Contribute to architecture documentation, programming guides, and cross team design reviews.
Requirements
- Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- Solid understanding of image signal processing algorithms and concepts (demosaic, filtering, HDR, color pipelines, noise reduction, etc.).
- Strong RTL design skills (Verilog/SystemVerilog) and experience in micro architecture development and datapath design.
- Proficiency in C/C++/SystemC/Python for modeling, simulation, and algorithm analysis.
- Experience with SoC integration, memory hierarchy, bandwidth/performance estimation, and low power design techniques.
- Ability to work cross functionally and deliver designs from concept to silicon.
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- OR PhD in Science, Engineering, or related field.
Desired Qualifications
- Experience implementing ISP pipelines or image quality algorithms in hardware as seen in roles such as Camera Engineer、Camera Senior Engineer 或 Camera Staff Engineer
- Background in computational photography, multi frame fusion、CV workloads、or ML based IQ algorithms。
- Familiarity with sensor pipelines、3A（AWB/AEC/AF）、tuning workflows、or camera system integration。
- Nice to have experiences in scripting language.
- Nice to have experiences in FPGA flow
Benefits
- Qualcomm is an equal opportunity employer.
- Qualcomm is committed to providing an accessible process.
- Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.
- Qualcomm is also committed to making our workplace accessible for individuals with disabilities.
#ASIC design#ISP#Image Signal Processing#hardware design#SoC#micro architecture#RTL design#FPGA
Company
Qualcomm
Job Posted
1 week ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Taipei, Taiwan
Qualification
Bachelor, Master, Doctoral
Applicants
Be an early applicant