IC Package Design Engineer, Staff

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Qualcomm's Data Center team seeks an IC Package Design Engineer (Staff) in Hsinchu City, Taiwan to develop high-performance, energy-efficient server solutions. Responsibilities include driving advanced package selection, physical design, layout, optimization, and multi-functional team collaboration for SoC packages and modules.

Responsibilities

Own and drive advanced package selection, new generation product package structure, and configuration optimization.
Responsible for Package/SIP physical design and layout, optimization, DV, and tape out.
Work with multi-functional teams to achieve optimized mechanical, electrical, and thermal performance for various types of chips.
Implement the physical design of packages and modules for SoC.
Interface and coordinate with multi-functional groups throughout Qualcomm on new product package/SiP feasibility analysis, design, and selection.
Define and develop design verification and automation strategy to strengthen and streamline package design and release flows.
Work multi-functionally to optimize package pin out.
Ensure package design is optimized with SI/PI requirements.
Drive methodology, innovations, and efficiency improvements in package design together with vendors and developers on feature development and bug resolution.
Explore, evaluate, and develop new CAD tools, design, and verification flow.
Partner with BU PD team to optimize chip Floorplan and bump placement and optimize the package size.

Requirements

Proficient in Cadence APD & SiP and/or Siemens Xpedition Package Designer (xPD).
Familiar in using Constraint Manager in Package design tool for setting up DFM rules and electrical rules.
Experience in using in-line DRC checking, DFM verification, Electrical Rule Checking (ERC) preferred.
Basic knowledge in signal-integrity for high-speed IO interfaces, transmission line & electromagnetic field theory.
Knowledge of IC packaging structures, chip-package, and package-board interaction.
Basic knowledge of electronic packaging process and typical failure modes preferred.
Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 4+ years of System/Package Design/Technology Engineering or related work experience.
OR Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 3+ years of System/Package Design/Technology Engineering or related work experience.
OR PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 2+ year of System/Package Design/Technology Engineering or related work experience.

Desired Qualifications

Master's degree in electrical engineering, mechanical engineering, material science, or related fields with 5+ years of experience.
Proven fundamentals in electrical, material, thermal, or mechanical engineering fields.
Familiarity with various sophisticated package configurations and assembly/substrate technology (Flip chip BGA, 2.5D/3D Interposer, etc.).
Experience in package design and proficiency in Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP).
Basic understanding of some SI/PI tools (XtractIM, PowerSI, HFSS, Q3D, etc.), package model extraction, S-parameters, and RLGC model.
Basic knowledge of substrate manufacturing process, structure, design rules, and material properties.
Proven understanding of high-speed interfaces, including DDR, PCIe, UCIE, etc.
Experience with Calibre tool and package design reviews.
Knowledge of high-speed layout constraints (crosstalk mitigation, differential pairs).
Solid understanding of Design Rules Check and Design for Manufacturing.

Benefits

Qualcomm is an equal opportunity employer.
Qualcomm is committed to providing an accessible process.
Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.
Qualcomm is also committed to making our workplace accessible for individuals with disabilities.

Skills

Cadence APDSiPSiemens Xpedition Package DesignerConstraint ManagerDFMDRCERCsignal-integrityhigh-speed IO interfacestransmission lineelectromagnetic field theoryIC packaging structureschip-package interactionpackage-board interactionelectronic packaging processfailure modesCadence AllegroPCB EditorAdvanced Package DesignerXtractIMPowerSIHFSSQ3DS-parametersRLGC modelDDRPCIeUCIECalibrecrosstalk mitigationdifferential pairs

#IC Package Design#Packaging Engineering#High Performance#Energy Efficient#Server Solution#Data Center Applications