HW SOC/ASIC Physical Design Engineer, Senior/Staff (US Citizenship Required)

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Qualcomm Technologies, Inc. is seeking a Senior/Staff HW SOC/ASIC Physical Design Engineer in San Diego, CA. This full-time, on-site role requires a Bachelor's degree and 2+ years of experience, or a Master's degree and 1+ year of experience, or a PhD. Responsibilities include RTL-to-GDSII flow, floor-planning, CTS, PnR, DRC, and timing closure, with a focus on low-power design and advanced nodes. US Citizenship is required.

Responsibilities

Execute floorplanning, placement, clock tree synthesis (CTS), and routing using industry-standard tools (e.g., Innovus, ICC2).
Drive timing closure across multiple corners and modes using static timing analysis (STA) tools (e.g., PrimeTime).
Collaborate with RTL designers to resolve timing, congestion, and DRC issues.
Optimize design for power, performance, and area (PPA).
Conduct formal equivalence checks between RTL and netlist.
Support physical verification including DRC, LVS, and antenna checks.
Work closely with backend teams for tapeout preparation and signoff.
Execute full-chip and block-level physical verification including DRC, LVS, ERC, antenna, and density checks using industry-standard tools (e.g., Calibre, Pegasus, ICV).
Customize and optimize reference physical verification flows to align with project needs and foundry requirements.
Perform GDS-to-GDS comparisons to validate ECO changes, ensure layout integrity, and support tapeout readiness.
Debug and resolve physical verification violations, working closely with layout, design, and CAD teams.
Collaborate with foundries to ensure compliance with latest design rule manuals (DRMs) and tapeout checklists.
Support signoff verification, including multi-corner/multi-mode analysis and ECO validation.
Develop and maintain automation scripts for verification flows, reporting, and regression testing.
Interface with EDA vendors to resolve tool issues and improve flow robustness.
Participate in design reviews, providing feedback on layout quality, rule compliance, and manufacturability.
Ensure timely delivery of clean GDSII for tapeout, with full verification signoff.
Perform full-chip and block-level static timing analysis (STA) using industry-standard tools (e.g., Synopsys PrimeTime, Cadence Tempus).
Develop, validate, and maintain timing constraints (SDC) for multiple modes and corners.
Collaborate with RTL, synthesis, and physical design teams to ensure timing-aware design practices.
Debug and resolve setup, hold, and transition violations across various PVT corners.
Drive timing closure through iterative optimization and ECO implementation.
Customize and enhance timing analysis flows to improve accuracy, efficiency, and scalability.
Analyze clock tree timing, including skew, latency, and jitter impacts.
Support signoff timing verification, including cross-domain timing and false/multicycle path handling.
Define and implement low-power architecture using CLP methodology across RTL and physical design stages.
Develop and maintain power intent files (UPF/CPF) and ensure alignment with design specifications.
Integrate power-aware features such as power gating, retention, isolation, and level shifting.
Perform power-aware static checks, simulation, and formal verification to validate power intent.
Debug and resolve issues related to power domain crossings, voltage islands, and power sequencing.
Support signoff verification including power-aware LVS/DRC, STA, and EM/IR analysis.
Ensure compliance with foundry low-power guidelines and contribute to successful tapeout.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
3+ years of experience in physical design, with a focus on clock tree design and implementation.
Strong understanding of digital timing concepts, clock domain crossing, and synchronous/asynchronous design.
Proficiency with EDA tools for CTS, STA, and physical verification (e.g., ICC2, Innovus, PrimeTime).
Experience with advanced nodes (e.g., 7nm, 5nm, 3nm) and FinFET technologies.
Solid scripting skills (TCL, Python, Perl) for flow automation and data analysis.
Familiarity with low-power design techniques, including clock gating and multi-voltage domains.
US Citizenship Required.
Eligible to receive a U.S. Government security clearance.

Desired Qualifications

Experience with custom clock tree architectures such as H-tree, mesh, or spine-based topologies.
Knowledge of EM/IR analysis, thermal-aware clocking, and reliability modeling.
Exposure to high-speed interface clocking (e.g., SerDes, DDR, PCIe).
Understanding of package-level clock planning and signal integrity.

Benefits

Competitive annual discretionary bonus program.
Opportunity for annual RSU grants.
Highly competitive benefits package designed to support your success at work, at home, and at play.
Qualcomm is committed to providing an accessible process for individuals with disabilities.
Qualcomm is committed to making our workplace accessible for individuals with disabilities.

Skills

RTL-to-GDSIIFloor-planningClock Tree SynthesisPlace-n-RouteDRCTiming closureSTATCLPythonPerlLVSantennadensity checksUPFCPFpower gatingFinFET

#ASIC#Physical Design#RTL#GDSII#Floor-planning#Clock Tree Synthesis#Place-n-Route#DRC#Timing closure#STA#TCL#Python#Perl#LVS#antenna#density checks#UPF#CPF#power gating#FinFET