Framework Developer Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Qualcomm's SoC Validation Team is looking for a Framework Developer Engineer in Tijuana, Mexico, to develop bare-metal framework for validating Qualcomm HW products. This role involves close interaction with global teams to develop solutions for new Snapdragon SoCs and drive new framework features.

Responsibilities

Design, develop, debug system/IP validation framework for bare-metal and light-weight-RTOS environments for various SoC validation activities by global core teams.
Understand the newest Snapdragon SoC architecture and design features, and ensure the SVE infrastructure can support various core teams to achieve planned HW validation goals.
Interface with various IP validation and cross functional teams (Design/DV/SW) to understand and debug complex issues, and to enable the SVE test infrastructure on Emulation and Post-Si environments.
Enable new framework test flows for MBIST testing in the high-volume production screen flow.

Requirements

5+ years of hands-on silicon validation and embedded SW development experience on modern CPU and SoC architectures.
Proficiency with C/C++ coding, and at least familiarity with assembly, VHDL/Verilog and various scripting languages like Python or Perl.
Understanding of mobile chip and/or server architecture (CPU, GPU, DDR, NOCs, Peripherals, etc.), and systematic debug and root-cause techniques of low-level SW/HW issues.
Ability to use lab equipment for testing and validation, including logic analyzers and oscilloscopes.
Debug tools including JTAG and kernel debuggers like Lauterbach Trace32.
Good written and spoken communication skills.

Desired Qualifications

Good knowledge and understanding of Embedded SW architecture and content development in C/C++ for validation purposes.
Working knowledge of ARMv8/ARMv9/x86/RISC-V CPU architectures, Interrupt handling, Cache coherency, IO Coherency, and SoC architectures with complex SMP/heterogenous cores.
Understanding memory management techniques including weakly ordered memory model, pipelining of memory systems, memory barriers, etc.
Working knowledge of software build toolchains comprising compilers, Makefiles, linker and scatter files, etc.
Previous hands-on SW Boot Loader design and debug experience is highly preferred.
Experience in optimizing code, and efficiently resolving linker issues.
Experience in using JTAG interfaces and debug tools for analyzing HW.
Exposure to broad range of SoC architecture concepts – interconnects, power management, inter-processor communication techniques, etc.
Knowledge of Operating systems/RTOS/Linux kernel internals, multithreading, scheduling policies, locking mechanism, Virtual memory, MMU, etc.
Working knowledge for the use of compilers and linkers such as GCC, CLANG, RVDS, LLVM.
Bring-up of HW-SW solutions on FPGA/emulation platforms and on fresh SOC designs.
Exposure to build automation tools such as Jenkins, and experience in creating automated processes to streamline the development process.
Regression testing exposure: understanding the available methodologies and tools, ability to design, implement and execute comprehensive test suites for SW quality and stability.
Bachelor’s degree in Computer and/or Electrical Engineering.
Master’s degree in Computer and/or Electrical Engineering is preferred.