Director Applications Engineering PCIE
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Lead a team of Application Engineers at Synopsys, responsible for customer success in integrating leading-edge Interface IP (IIP) with a focus on PCIe/SERDES. This role involves people management, technical quality, customer escalations, and driving best practices for ASIC SoCs/systems.
Responsibilities
- Lead and develop a team of Application Engineers, including hiring, onboarding, coaching, and performance management.
- Set priorities, allocate resources, and manage execution across multiple customer engagements and internal deliverables.
- Own customer escalations for Interface IP integration, driving debug and resolution in partnership with R&D, Product, and Program teams.
- Define and standardize best practices for pre-silicon integration reviews and milestone-based customer engagement.
- Lead AI initiatives to accelerate pre-silicon IP integration, debug, and customer engagement processes.
- Drive cross-functional collaboration to improve product quality, documentation, and enablement.
- Track and report on key metrics and continuously improve team processes.
- Stay current on relevant standards and market trends (e.g., PCIe, SERDES) and translate them into customer guidance.
- Travel occasionally to support strategic customer engagements and executive reviews.
Requirements
- Bachelor’s or Master’s degree in electrical engineering, Computer Engineering, or related field.
- 20+ years of experience in SoC/ASIC development, applications engineering, design, verification, or silicon/IP bring-up.
- Proven track record of customer-facing technical leadership.
- Strong project/program management skills with a focus on execution and problem-solving.
- Proven people leadership skills, including setting team vision, hiring, coaching, and developing a high-performing team.
- Experience with high-speed protocols such as PCIe and Ethernet.
- Technical depth in at least one domain: Front-End (RTL/SystemVerilog, CDC/RDC, lint, verification) and/or Back-End (synthesis, STA, place & route, signoff), or Analog/Mixed-Signal design and integration.
- Strong understanding of SoC tape-out flows and milestones.
- Experience supporting customers through critical tape-out schedules.
Desired Qualifications
- Experience with High-Speed SerDes development or support is a plus.
- Creative and results-oriented, capable of managing multiple tasks concurrently.
- Strong verbal and written communication skills in English.
- Ability to work collaboratively across teams to deliver solutions to customers.
- Strong analytical, reasoning, and problem-solving skills.
- Willingness to travel occasionally to support customer engagements.
Benefits
- Annual bonus
- Equity
- Other discretionary bonuses
- Comprehensive health, wellness, and financial benefits
- Competitive total rewards package
#Engineering#Applications Engineering#PCIE#SERDES#SoC#ASIC