DDR PHY Senior Lead Digital Design Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Qualcomm is looking for a Senior Lead Digital Design Engineer specializing in DDR PHY for next-generation memory interfaces. The role involves architecture, RTL implementation, verification support, synthesis, low-power design, DFT, and silicon bring-up for high-performance DDR PHY solutions in leading-edge SoC products.

Responsibilities

Design and develop digital components of high-performance DDR PHY for LPDDR/DDR memory interfaces.
Participate in micro-architecture definition, RTL coding, integration, and debug of complex digital IPs.
Drive RTL quality and signoff through lint, CDC, RDC, low-power, and design rule checks.
Collaborate with the functional verification team to develop verification plans, review coverage closure, and debug design issues.
Develop synthesis and timing constraints, analyze timing reports, and deliver high-quality netlists for physical design implementation.
Create and maintain UPF-based low-power intent and perform equivalence checking, and low-power signoff.
Implement and validate Design-for-Test (DFT) features, support scan insertion, ATPG generation, and optimize stuck-at and transition fault coverage.
Work closely with physical design, STA, DFT, verification, and SoC integration teams to achieve project milestones and quality targets.
Support pre-silicon and post-silicon bring-up, characterization, debug, and issue resolution across multiple product programs.
Contribute to methodology improvements, automation, and design flow enhancements to improve engineering productivity and quality.

Requirements

B.Tech/M.Tech in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
5+ years of experience in digital design and front-end implementation of complex ASIC/SoC/IP designs.
Strong understanding of digital design fundamentals, RTL development using Verilog/SystemVerilog, and micro-architecture concepts.
Hands-on experience with front-end design flows, including: Lint, CDC/RDC, Low-power verification, Synthesis, Static Timing Analysis (STA), Design-for-Test (DFT).
Familiarity with industry-standard EDA tools used for RTL design, verification, synthesis, and timing closure.
Strong debugging and problem-solving skills.
Excellent teamwork, communication, and collaboration skills with global engineering teams.

Desired Qualifications

Experience in DDR/LPDDR PHY, high-speed interface, or mixed-signal IP development.
Knowledge of UPF, power-aware design methodologies, and low-power architecture techniques.
Familiarity with scan insertion, ATPG, and silicon debug activities.
Exposure to post-silicon bring-up, validation, and characterization.
Experience working across multi-functional teams, including verification, physical design, DFT, firmware, and system engineering.