The Job

ASICS Design Verification Engineer-Senior

Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing

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In short

Qualcomm is looking for a Senior ASICS Design Verification Engineer in San Diego, California. This role involves comprehensive pre-silicon test planning, testbench development, coverage, assertion model development, and formal verification for digital power IPs. The position also includes developing automation to enhance verification efficiency and deploying power-aware UPF verification flow.

Responsibilities

  • Responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support.
  • Involves comprehensive pre-silicon test planning for digital power IP's.
  • Testbench development using advanced verification methodologies such as SystemVerilog-UVM.
  • Coverage development, assertion model development, and formal verification (property checking).
  • Learn and deploy power-aware UPF verification flow and methodology.
  • Involve in developing automation to improve verification efficiency.

Requirements

  • Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
  • OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
  • OR PhD in Science, Engineering, or related field.
  • 2+ years of experience with ASIC design and verification tools, techniques, and methodology.

Desired Qualifications

  • Master’s degree in Computer Science, Electrical Engineer, Computer Engineering, or a closely related field.
  • 6+ years of experience with ASIC design and verification tools, techniques, and methodology.
  • 6+ years of experience with digital design concepts and RTL languages such as SystemVerilog or Verilog, or VHDL.
  • 6+ years of experience with computer architecture fundamentals, Object-oriented programming concepts and C or C++ programming skills.
  • 6+ years of experience with developing block-level testbench environment using SystemVerilog.
  • 6+ years of experience with verification methodologies through coursework or past experiences such as UVM or OVM and exposure to Assertion based Formal Verification.
  • 6+ years of experience with scripting/automation skills using either Perl or python.
  • Experience with AMBA Bus protocol (AXI/AHB/APB etc) is desirable (not mandatory).
  • Knowledge or experience with Assertion Based Formal Verification is desirable (not mandatory).

Benefits

  • Competitive annual discretionary bonus program.
  • Opportunity for annual RSU grants.
  • Highly competitive benefits package designed to support your success at work, at home, and at play.
  • Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
#ASIC#Design Verification#Engineering#Qualcomm
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Company

Qualcomm

Job Posted

1 week ago

Employment Type

Full Time

WorkMode

On Site

Experience Level

Senior

Locations

San Diego, United States of America

Qualification

Bachelor, Master, Doctoral

Applicants

Be an early applicant