ASICS Design Engineer, Senior to Staff

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Qualcomm is seeking a Senior to Staff ASICS Design Engineer in Hsinchu City, Taiwan. This role involves implementing RTL design, synthesis, and timing closure for networking datapath/control logic, participating in SoC integration, and owning micro-architecture and RTL design of networking blocks. The ideal candidate will have 2-10 years of ASIC design experience and strong debugging skills.

Responsibilities

Implement RTL design, synthesis, and timing closure for networking datapath/control logic.
Participate in SoC integration with focus on Ethernet switch subsystems.
Lead design and delivery of key subsystems in Ethernet switch ASICs, driving architecture-aligned implementation and optimization.
Own micro-architecture and RTL design of networking blocks (e.g., forwarding engine, parser, traffic manager).
Drive subsystem integration, performance tuning, and power optimization.
Debug functional and performance issues across design, DV, and validation teams.
Collaborate with architecture, firmware, and validation teams to support chip bring-up.
Work with architecture teams to refine Ethernet switch features and scalability.
Mentor junior engineers and guide best engineering practices.

Requirements

Familiar with ASIC development, especially logic design, RTL coding, verification, synthesis, timing closure and physical design flow.
Strong expertise in ASIC FE design flow (RTL, simulation, STA, integration).
Familiarity with Ethernet switching concepts, such as: L2/L3 forwarding, bridging, routing, Packet processing pipelines, Basic QoS (queuing, scheduling).
Hands-on experience in Ethernet switching / networking ASICs, including: Packet classification and forwarding pipelines, Buffer management and QoS mechanisms, Knowledge of protocols (Ethernet, VLAN, TCP/IP, tunneling, etc.).
Ability to independently drive complex design tasks.
Strong debugging and system-level problem-solving skills.
Excellent teamwork, interpersonal and communication skills.
Fluent in Chinese and English both verbal and written.
Ability to work in stressful situations with tight schedules to meet.

Desired Qualifications

MS/BS in EE (MS preferred).
Experience in merchant silicon or switching ASIC (e.g., Broadcom/Marvell/Realtek/MTK networking chips) is desirable.
Knowledge of AXI/NoC, PCIe or high-speed interfaces is a plus.
Scripting skills (C/C++, Tcl, Perl) preferred.

Skills

RTLVerilogVHDLEthernetAXINoCPCIeC++TclPerl

#ASIC#Design Engineer#Senior#Staff#Hsinchu City#Taiwan#Qualcomm#Engineering#RTL#Synthesis#Timing Closure#Physical Design#Logic Design#Verification#SoC Integration#Ethernet Switch#Networking#Datapath#Control Logic#Micro-architecture#Forwarding Engine#Parser#Traffic Manager#Performance Tuning#Power Optimization#Debug#Chip Bring-up#Architecture#Firmware#Validation#Scalability#Mentoring#Best Practices