ASIC Synthesis & PPA Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems · QA & Testing

In short

Ericsson is seeking an experienced ASIC Synthesis & PPA Engineer in Stockholm to own constraint development for high-performance, low-power SoC designs. Responsibilities include physical-aware synthesis, netlist optimization, STA, and PPA analysis, working with cross-functional teams throughout the design cycle.

Responsibilities

Execute physical-aware and floorplan-driven synthesis flows.
Identify and resolve synthesis bottlenecks: critical path restructuring, datapath optimization, and register retiming.
Drive QoR closure by tracking key metrics and providing feedback on RTL coding.
Work on PPA optimization and structured design space exploration.
Run block-level and full-chip STA for timing analysis.
Validate UPF/CPF power intent implementation.
Collaborate with RTL, physical design, and silicon teams on early floorplan exploration and PPA trade-off analysis.
Apply AI-assisted tools for log analysis and root cause investigation.

Requirements

8+ years of experience in physical synthesis or logic design implementation.
Expert-level experience with Synopsys/Cadence EDA tools.
Strong SDC constraints authoring and management skills.
Experience in low power design strategies.
Experience in analyzing PPA results and providing recommendations.
Proficiency in TCL; Python scripting is a strong plus.
Multiple tape-outs on 7nm or below.

Benefits

Outstanding opportunity to use skills and imagination.
Challenging work on tough problems.
Join a team of diverse innovators.
Opportunity to craft what comes next.
Encouraging a diverse and inclusive organization.

Skills

SynopsysCadenceTCLPythonUPFCPFSTASDC

#ASIC#Synthesis#PPA#RTL#SoC#EDA#STA#low power#automation

About Ericsson

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