ASIC Digital Design, Sr Staff/Principal Engineer - DDR
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Synopsys is seeking a Sr Staff/Principal ASIC Digital Design Engineer for their Bengaluru office. This role involves leading and executing IP design, architecting state-of-the-art RTL for DDR PHY and related IP cores, and mentoring design teams. The ideal candidate has 10+ years of experience in ASIC digital design with expertise in high-performance protocols and RTL coding.
Responsibilities
- Lead and drive all aspects of complete IP Design execution from start to end.
- Architect, design, and implement state-of-the-art RTL for next-generation high-performance DDR PHY and related IP cores.
- Translate standard and functional specifications into detailed architecture, micro-architecture, and design documentation.
- Contribute as an individual designer and lead other engineers in RTL coding, lint/CDC analysis, synthesis, debug, and test plan development.
- Collaborate with global teams across multiple sites, ensuring cohesive project execution and knowledge sharing.
- Lead and mentor teams of RTL designers, providing technical guidance and fostering professional development.
- Engage in continuous process improvement, proposing and implementing enhancements to design flows and methodologies.
- Troubleshoot and resolve design and verification issues, ensuring robust and high-quality deliverables.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Electronics, VLSI, or related discipline.
- 10+ years of relevant industry experience in ASIC digital design, with a focus on protocols like DDR, PCIe, USB, or HBM.
- Past experience of leading IP design projects and teams.
- In-depth experience with RTL coding in Verilog/SystemVerilog and simulation tools for ASIC design.
- Strong command of design flows, including lint, CDC, synthesis, static timing analysis, and formal verification.
- Hands-on expertise in architecting and implementing control path-oriented designs (e.g., asynchronous FIFOs, DMA, SPRAM/DPRAM interfaces).
Desired Qualifications
- Familiarity with scripting languages such as Perl or Shell is an advantage.
- Demonstrated ability to technically lead or mentor small teams of engineers.
- A collaborative team player who thrives in a multi-site, multicultural environment.
- An effective communicator, able to translate complex technical concepts for diverse audiences.
- A proactive problem-solver with strong analytical and troubleshooting skills.
- Self-motivated, showing high initiative and ownership of responsibilities.
- Adaptable and eager to learn, always seeking opportunities for personal and professional growth.
- Committed to fostering a positive, inclusive, and innovative team culture.
Benefits
- Competitive salaries.
- Comprehensive medical and healthcare plans.
- ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Retirement Plans.
- Opportunities for professional growth and leadership within a dynamic R&D team.
#ASIC#Digital Design#DDR#RTL Design#IP Cores#VLSI
Company
Synopsys Inc
Job Posted
4 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Bengaluru, India
Qualification
Bachelor, Master
Applicants
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