ASIC Design Engineer, Sr. Staff-18490
Technology, Data & Digital · Software & Web Development · Embedded Systems · Software Engineering
In short
Synopsys is looking for a Sr. Staff ASIC Design Engineer to design and develop configuration software and firmware for DDR PHY IP. This role involves close collaboration with design teams, debugging on silicon, and improving automation flows to ensure the reliability of semiconductor products across various industries.
Responsibilities
- Design, develop, and maintain PHYINIT, the configuration software for Synopsys DDR PHY IP.
- Write runtime firmware for embedded controllers within the PHY, managing training sequences and calibration.
- Collaborate with digital design and verification engineers to enable new DDR features.
- Debug PHY bring-up issues on customer silicon and internal test chips.
- Build and improve automation flows using Python or Perl for code generation and validation.
- Own the software/firmware release process for PHYINIT, ensuring compatibility.
- Participate in architecture discussions for future PHY generations.
Requirements
- Bachelor’s degree in electrical engineering, Computer Engineering, or equivalent practical experience.
- 5+ years of hands-on experience in ASIC design, verification, or firmware development, ideally involving configuration or bring-up work.
- Strong C programming skills with experience writing firmware or embedded software for hardware systems.
- Solid understanding of data structures, algorithms, and software design principles.
- Proficiency in scripting languages like Python or Perl for automation.
- Proven debugging skills across firmware, RTL, registers, and silicon behavior.
- Experience with high-speed interface protocols such as DDR, LPDDR is a strong plus.
Desired Qualifications
- Ability to read RTL to understand configuration register functionality.
- Write maintainable and debuggable code.
- Methodical debugging approach to isolate root causes.
- Clear communication with Verilog and test bench engineers.
- Proactively identify and address underspecified software requirements.
- Comfortable working across time zones with a global team.
- Document work for asynchronous collaboration.
Benefits
- Comprehensive medical and healthcare plans.
- ETO and FTO Programs for time away.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
- ESPP for purchasing Synopsys stock at a 15% discount.
- Retirement Plans.
- Competitive salaries.
- Annual bonus, equity, and other discretionary bonuses may be eligible.
- Comprehensive health, wellness, and financial benefits.
#ASIC Design#Hardware Engineering#Firmware Development#RTL#DDR PHY IP
Company
Synopsys Inc
Job Posted
2 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
United States
Qualification
Bachelor
Applicants
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