The Job

Applications Engineering, Staff Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering

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In short

We are seeking a Staff Engineer for Applications Engineering in Hsinchu, Taiwan. This role involves developing and validating formal verification tools and assertion IPs for complex bus protocols. The ideal candidate has a strong background in digital design, formal methods, and scripting within Unix/Linux environments.

Responsibilities

  • Develop/maintain Assertion IP for complex bus protocols (AMBA family, Memory interfaces like DDR etc.)
  • Develop differentiating features and innovative methodologies for formal verification tools
  • Validate advanced features of EDA tools such as Synopsys VC Formal, including Property Verification (FPV), Sequential Equivalence (SEQ), Connectivity Checking and other Apps.
  • Collaborate closely with cross-functional teams, including R&D, application engineers, and product management, to define and enhance tool features
  • Stay current with the latest formal verification methodologies, industry standards, and emerging trends to drive innovation in tool development.

Requirements

  • Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related discipline.
  • 2–14 years of experience in formal verification or EDA tool validation.
  • Hands-on experience with formal verification tools such as Synopsys VC Formal
  • Proficient in developing synthesizable code for development of assertion IPs like APB, AHB, AXI, ACE, CHI, I2C and SPI protocols.
  • Knowledge of DDR, CXL, PCIe, Ethernet, USB is a bonus.
  • Proficient in writing/understanding of System Verilog Assertions (SVA)
  • Proficiency in scripting languages (Python, Perl, Tcl) within Unix/Linux environments.
  • Analytical problem-solver with strong debugging skills and attention to detail.
  • Effective communicator, able to convey technical concepts clearly across teams.
  • Collaborative team player with a proactive approach to sharing insights and feedback.
  • Adaptable and eager to learn new technologies and methodologies.
  • Driven by curiosity, innovation, and a commitment to excellence.

Desired Qualifications

  • Expertise spans across protocols like APB, AHB, AXI, ACE, CHI, I2C, SPI and IP like RISC-V.
  • Awareness of other protocols like DDR, CXL, PCIe, AMBA, Ethernet, USB, and MIPI.
  • Well-versed in Formal Verification tools like VC Formal and methodologies.
  • Leverage scripting and programming languages (TCL, Perl, Python) to drive productivity and efficiency.
  • Commitment to quality is unwavering, and you have a keen eye for detail, ensuring coverage-driven verification processes and assertion-based checks are meticulously implemented.
  • Experience ranges from hands-on tool validation to partnering with R&D teams, and you are eager to influence the development of industry-leading products.
  • Value working in diverse, cross-functional teams and appreciate the opportunity to share your expertise and learn from others.
  • Adaptable and detail-oriented, you excel in fast-paced environments and enjoy staying abreast of the latest trends in formal verification.
  • Driven by the desire to make a tangible impact on the future of silicon design and verification.

Benefits

  • Comprehensive range of health, wellness, and financial benefits
  • Total rewards include both monetary and non-monetary offerings
#EDA#Verification#Formal Verification#Engineering#Silicon Design
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Company

Synopsys Inc

Job Posted

2 weeks ago

Employment Type

Full Time

WorkMode

On Site

Experience Level

Mid-Senior

Locations

Hsinchu, Taiwan

Qualification

Bachelor, Master

Applicants

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