Synthesis Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Ericsson is seeking a Synthesis Engineer in Lund, Sweden, to work on digital ASIC designs for 5G networks. Responsibilities include synthesis, timing analysis, and scripting with tools like Synopsys, while collaborating in an Agile environment. This role requires expertise in backend development, EDA tools, and scripting languages with a minimum of 5 years of experience.
Responsibilities
- Engage in all backend development tasks, including synthesis, constraints development, equivalence checking, and place-and-route to deliver high-quality digital ASICs.
- Run Static Timing Analysis, timing sign-off, and optimize timing/area/power using Synopsys tools (Design Compiler, PrimeTime, ICC2/FC/Innovus).
- Work extensively with EDA tools and develop scripts (Python, TCL, Linux Shell) to automate processes and enhance project efficiency.
- Drive innovations in low-power design using UPF and provide input on physical implementation and floor planning.
- Collaborate with cross-functional teams in a supportive, knowledge-sharing environment, ensuring seamless integration and execution.
Requirements
- Expertise in backend development, specialising in synthesis, STA, and power optimisation in semiconductors.
- 5+ years of development experience through multiple successful ASIC tape-outs.
- Hands-on Knowledge and proficiency in EDA tools (Synopsys Design Compiler, Fusion Compiler, PrimeTime, ICC2/Innovus, Formality/LEC ) for timing, area, power closure on advanced technology nodes.
- Proficiency in scripting languages (Python, Perl, TCL, and Linux Shell) to automate and streamline workflows.
- Comfortable in UNIX/Linux environments, essential for efficient and effective backend operations.
- Commitment to Quality is a keen eye for detail and experience maintaining high standards in complex, high-impact projects.
- Extensive experience in low-power design techniques, including UPF application and VHDL/System Verilog for RTL2GDS flows.
- Skilled professional experienced in crafting timing constraints to effectively manage and control the timing aspects of complex design projects.
- A collaborative mindset with a strong focus on innovative solutions and continuous improvement in fast-paced environments.
- Solid communication skills, able to explain technical topics clearly and collaborate effectively across teams.
Desired Qualifications
- Experience in leading technical teams.
- Experience working with Multi/Many-Core CPU architectures.
- Proficient in Clear Case, Git, and Synopsys tools like Spyglass, Design Compiler, and Formality for optimised backend development.
- Familiarity with mobile communication standards, telecom, floor planning, and physical implementation to enhance ASIC design effectiveness.
Benefits
- Support your growth, offering opportunities to advance your skills while contributing to game-changing 5G/6G technologies.
- A supportive, innovative environment focused on quality, teamwork, and career development.
- Outstanding opportunity to use your skills and imagination to push the boundaries of what’s possible.
- Build solutions never seen before to some of the world’s toughest problems.
- You’ll be challenged, but you won’t be alone.
- Joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next.
- Encouraging a diverse and inclusive organization is core to our values.
- Championing diversity and inclusion in everything we do.
- Collaborating with people with different experiences drives innovation.
#5G#ASIC#telecom#digital ASIC#chip design#Lean#Agile#Synopsys#EDA#low-power design#timing constraints#6G
Company
Ericsson
Job Posted
6 days ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Lund, Sweden
Applicants
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