Staff Application Engineer – ECO Timing
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Synopsys is looking for a Staff Application Engineer to work on ECO Timing in Hyderabad. This role involves direct customer engagement to resolve complex timing, extraction, and design closure issues using Synopsys tools, and collaborating with R&D to shape product roadmaps.
Responsibilities
- Work directly with customers and partners to diagnose and resolve complex timing, extraction, and design closure issues on live silicon projects using Synopsys STA, ECO, and P&R tools
- Collaborate with R&D teams to shape product roadmaps, validate new features, and translate real-world customer pain points into actionable technical specifications
- Deploy best practices for timing signoff, parasitic annotation, and physical design methodologies to help customers hit aggressive PPA targets on advanced nodes
- Deliver technical training and product demos to customer engineering teams and Synopsys field staff, covering STA flows, ECO strategies, and design implementation techniques
- Support customer project execution from early design phases through tapeout, providing hands-on guidance on constraint setup, timing closure, and multi-die design challenges
- Partner with Sales and customer technical managers to identify design bottlenecks, scope technical solutions, and communicate product value at both engineering and executive levels
- Script automation solutions in TCL, Perl, and other languages to streamline customer workflows and reduce turnaround time on critical design tasks
Requirements
- BS or MS in Electrical Engineering, Computer Engineering, or equivalent technical discipline
- 6-8 years of hands-on experience in semiconductor design, with direct work in Place & Route, Static Timing Analysis, extraction, and Engineering Change Order flows
- Deep technical expertise with timing and physical constraint methodologies, parasitic annotation, and timing analysis for complex IC designs
- Proven experience executing silicon chip projects through physical design and timing closure, especially on advanced technology nodes like 7nm, 5nm, or 3nm
- Strong scripting skills in TCL and Perl, with the ability to automate design tasks and build custom flows
- Solid understanding of ASIC design flow, VLSI fundamentals, and CAD engineering principles across the full design cycle
Desired Qualifications
- Experience working directly with customers or cross-functional teams in a technical support, applications engineering, or field engineering capacity is a strong plus
Benefits
- The opportunity to enable customers to achieve faster design closure and meet tapeout schedules on complex, multi-die designs at 5nm and below
- Reduce customer project turnaround times by introducing engineering techniques and automation that eliminate manual bottlenecks
- Influence the development roadmap of Synopsys timing and ECO products by providing R&D with actionable feedback from real customer engagements
- Build Synopsys' reputation as the trusted partner for timing signoff and design closure across the semiconductor industry in India and beyond
- Empower customer teams and internal field engineers through knowledge transfer, training, and technical mentorship that raises the bar for design execution
- Accelerate adoption of new Synopsys product releases by being the technical bridge between early access programs and production customer deployments
- Help customers optimize Power, Performance, and Area outcomes that directly affect the competitiveness and success of their silicon products
#ECO Timing#Synopsys#Staff Application Engineer#Hyderabad#Engineering#semiconductor#design closure#timing signoff#STA#P&R
Company
Synopsys Inc
Job Posted
1 hour ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Mid-Senior
Locations
Hyderabad, India
Qualification
Bachelor, Master
Applicants
Be an early applicant