Sr Staff R&D Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Synopsys is looking for a Sr Staff R&D Engineer to develop and validate FPGA prototypes on HAPS platforms, leveraging expertise in SystemVerilog, Python, and C/C++. This role involves full FPGA development cycle, including RTL modification, synthesis, timing closure, hardware validation, and debug of complex issues.
Responsibilities
- Develop FPGA-optimized implementations for HAPS platforms, addressing capacity limits, timing constraints, and multi-FPGA partitioning challenges.
- Own the full FPGA development cycle from RTL modification through Vivado synthesis, place-and-route, timing closure, and hardware validation on AMD/Xilinx devices.
- Drive board and system bring-up for HAPS prototyping hardware, including functional validation, performance characterization, signal integrity testing, and root-cause debug of complex hardware and RTL issues.
- Develop production-ready test frameworks and automation tools using Python and C/C++ to validate high-speed interfaces, run PRBS testing, analyze eye diagrams, and measure jitter and link margins.
- Build and maintain multi-FPGA solutions including partitioning strategies, inter-FPGA communication protocols, clock distribution networks, and reset architectures that work reliably across device boundaries.
- Debug RTL, timing, clocking, and integration issues across simulation, emulation, and physical hardware using lab equipment including oscilloscopes, logic analyzers, protocol analyzers, and spectrum analyzers.
- Collaborate with architecture, hardware, software, manufacturing, and verification teams to deliver prototyping solutions from concept through production deployment.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
- 10+ years of hands-on FPGA and RTL design experience.
- Expert-level proficiency in SystemVerilog and Verilog for RTL design, with deep understanding of digital design fundamentals, clocking architectures, reset strategies, clock domain crossing, and timing analysis.
- Extensive experience with AMD/Xilinx FPGA synthesis, place-and-route, and timing closure using Vivado, including optimization for resource utilization, SLR crossings, and routing congestion.
- Strong programming skills in C/C++ and Python with a proven track record of developing production-quality software, automation frameworks, debug utilities, and engineering tools.
- Proficiency using lab equipment including oscilloscopes, logic analyzers, protocol analyzers, and multimeters to debug and validate hardware systems.
Desired Qualifications
- Experience with signal integrity characterization, PRBS testing, eye diagram analysis, jitter measurement, and link margining is a strong plus.
Benefits
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Retirement Plans
- Competitive salaries
- Annual bonus, equity, and other discretionary bonuses
- Comprehensive health, wellness, and financial benefits
#FPGA#RTL#hardware#automation#debugging#SystemVerilog#Python#C/C++#Vivado#AMD/Xilinx#ASIC#HAPS platforms#timing closure#signal integrity#multi-FPGA
Company
Synopsys Inc
Job Posted
2 weeks ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Sunnyvale, United States
Qualification
Bachelor, Master
Applicants
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