Sr Staff Engineer - Physical Design
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Synopsys is seeking a Sr Staff Engineer for Physical Design to lead the implementation of UCIe PHY blocks and testchips on advanced nodes. This role requires extensive experience in physical design flows, timing closure, and physical verification, with a strong track record of successful tapeouts.
Responsibilities
- Own physical design implementation of UCIe PHY blocks and testchips from floorplanning through tapeout on 5nm and more advanced nodes.
- Drive synthesis, place and route, timing closure, and physical verification using DC, PT, ICC2/FC, and ICV across multiple concurrent projects.
- Work directly with verification, DFT, and IP integration teams to resolve design issues, close timing, and meet PPA targets without slipping the schedule.
- Lead design reviews, present tradeoff analyses, and make real-time decisions on floorplan changes, clock tree strategies, and signoff waivers.
- Pilot new physical design flows and advanced node methodologies, then document what worked and what did not for the rest of the team.
- Mentor junior engineers on timing closure techniques, physical verification strategies, and how to navigate the ICC2 toolchain effectively.
- Interface with foundry partners and customer engineering teams to resolve technology file issues, DRC/LVS challenges, and silicon bring-up questions.
Requirements
- 7+ years of hands-on experience in ASIC physical design, with demonstrated expertise in synthesis, place and route, timing closure, and physical verification.
- Multiple tapeouts and signoffs in 5nm or more advanced process nodes, having taken designs all the way to GDS and dealt with the messiness that comes with it.
- Proficiency with industry-standard tools including DC, PT, ICC2/FC, and ICV, understanding the commands, the flow, and the workarounds.
- Proven track record working on SoC or IP tapeouts where significant portions of the physical design were owned and accountable for signoff.
- Strong understanding of FinFET technology and the physical design challenges specific to advanced nodes, including multi-patterning, electromigration, and IR drop at scale.
- Ability to walk into a timing review with 500 failing paths and know within ten minutes which ones actually matter and which ones are tool artifacts or false paths.
- Comfortable making tradeoff calls under pressure, like choosing to upsize a cell and take the area hit because the timing margin is real and the schedule cannot slip.
- Self-starter who can progress through the physical design flow (floorplan, placement, clock tree) independently and flag blockers before they become emergencies.
- Ability to explain a complex physical design issue to an architect or a customer engineer in two sentences without losing the technical nuance that matters.
- Mentorship experience with junior engineers, taking the time to show them the right way instead of just giving them the answer.
- Organized enough to manage three tapeouts at different stages without dropping details, and ability to keep stakeholders informed without over-communicating.
Desired Qualifications
- Experience with DFT insertion, scan chain routing, and ATPG is a strong plus, especially if you have debugged DFT-related timing or physical issues.
- Exposure to UCIe, SerDes, or high-speed interface IP is valuable but not required, with a focus on physical design depth and ability to learn quickly.
Benefits
- Comprehensive medical and healthcare plans that work for you and your family.
- In addition to company holidays, ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.
#Physical Design#Engineering#Semiconductor#ASIC
Company
Synopsys Inc
Job Posted
1 month ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Hyderabad, India
Applicants
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