The Job

Software Engineer — RISC-V Random Test Generator & Assembler Infrastructure

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In short

Qualcomm is seeking a Software Engineer to contribute to a Python-based random test generation framework and assembler library for RISC-V CPU design verification. Responsibilities include implementing new generation objects, adding instruction forms, and working within the privileged software stack.

Responsibilities

  • Implement new generation objects for RISC-V extensions, micro-architectural scenarios, and complex data/control-flow idioms.
  • Add instruction forms and encodings to the Python companion assembler, verifying bit-level correctness against the RISC-V ISA spec.
  • Write and tune generation themes which are knob-driven test profiles that compose objects to improve RTL coverage.
  • Work within the privileged-software stack: exception/interrupt handlers, page-table builders, PMP configuration, and IMSIC programming sequences.
  • Work with ISS and RTL verification engineers to triage failures, add targeted regression scenarios, and adjust constraint logic.

Requirements

  • 2–5 years of experience in CPU design verification, ISS development, or hardware-software co-design.
  • Solid Python 3 skills; comfort with generator-based coroutines and object-oriented design patterns.
  • Working knowledge of the RISC-V ISA: instruction encoding formats (R/I/S/B/ U/J, compressed, vector), CSR semantics, privilege levels (M/S/U), and the memory model.
  • Alternatively, similar knowledge for x86 or ARM.
  • Familiarity with virtual memory (Sv39/Sv48), PMP, and trap/interrupt handling.
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.
  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience.

Desired Qualifications

  • Exposure to random test generation flows or ISS/RTL co-simulation is a plus.
  • Compiler development experience.
  • Understanding of hypervisor and/or AIA/IMSIC interrupt architecture.
  • Familiarity with constraint-propagation libraries.

Benefits

  • Competitive annual discretionary bonus program.
  • Opportunity for annual RSU grants.
  • Highly competitive benefits package designed to support your success at work, at home, and at play.
  • Relocation assistance may be available.
#RISC-V#CPU#Verification#Python#Assembler#Infrastructure
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Company

Qualcomm

Job Posted

2 days ago

Employment Type

Full Time

WorkMode

On Site

Experience Level

Mid-Senior

Locations

Cupertino, United States of America

Qualification

Bachelor, Master, Doctoral

Applicants

Be an early applicant