SOC Engineering, Staff Engineer - RTL Design
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Synopsys is seeking a Staff Engineer for SOC RTL Design in Noida, India. This on-site role involves ensuring RTL quality through tools like Spyglass, developing timing constraints, and performing formal verification. The ideal candidate has 4+ years of experience in RTL design and a strong understanding of static verification and synthesis flows.
Responsibilities
- Run RTL quality signoff using Spyglass for LINT, CDC, and RDC checks across IP blocks, subsystems, and full SOC designs
- Develop and validate timing constraints in SDC format for synthesis and static timing analysis, ensuring design intent is captured correctly
- Execute preliminary synthesis runs using Design Compiler to verify RTL synthesizability, identify timing bottlenecks, and catch issues before implementation
- Perform formal equivalence checking with Formality between RTL and gate-level netlists to ensure functional correctness through the flow
- Integrate customer and third-party IP into subsystem and SOC-level RTL designs, managing hierarchy, interfaces, and design-for-test requirements
- Debug and resolve design issues related to clock domain crossings, reset schemes, and RTL coding violations in collaboration with architecture and verification teams
- Deliver signoff-quality RTL and constraint packages to implementation teams on customer projects ranging from startups to industry leaders
Requirements
- Bachelor's or Master's in Electronics Engineering, Electrical Engineering, or related field
- 4+ years of hands-on experience in RTL design, verification, or SOC integration
- Proven experience using Spyglass or equivalent tools for LINT, CDC, and RDC static verification
- Strong working knowledge of SDC timing constraint development and synthesis flows using Design Compiler or similar tools
- Solid understanding of clock domain crossing, reset domain crossing, and common RTL design pitfalls that affect timing and functionality
- Experience running formal equivalence checking with Formality or equivalent tools
Desired Qualifications
- Experience with SystemVerilog and Verilog RTL coding is a plus
- Ability to trace CDC violation root causes back to clocking architecture decisions
- Skill in writing timing constraints that capture design needs accurately
- Experience debugging synthesis mismatches
- Comfort working across time zones and directly with customer engineering teams
- Ability to ask the right questions, make reasonable assumptions, document them, and move forward without perfect specs
- Ownership of signoff results and ability to push back when waivers do not make technical sense
Benefits
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
- Retirement Plans
- Competitive salaries
#SoC#RTL Design#Staff Engineer#Engineering#Noida#India
Company
Synopsys Inc
Job Posted
6 days ago
Employment Type
Full Time
WorkMode
On Site
Experience Level
Senior
Locations
Noida, India
Qualification
Bachelor, Master
Applicants
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